E2U0053-28-81
¡ Semiconductor
MSM7728
¡ Semiconductor
Single Rail Linear CODEC
This version: Aug. 1998
MSM7728
Previous version: Apr. 1997
GENERAL DESCRIPTION
The MSM7728 is a single-channel linear CODEC CMOS IC for voice signals that contains filters
for A/D and D/A conversions.
Designed especially for a single-power supply and low-power applications, the device is
optimized for applications for the analog interfaces of audio signal processing DSPs and digital
wireless systems.
The analog outputs include the speaker drive output, earphone drive output and ringer output.
Therefore, the sound interface can be configured with a few external circuits.
FEATURES
• Single power supply
: 2.5 V to 3.6 V
• Low power consumption
Operating mode
: 36 mW Typ.
Power down mode
: 0.003 mW Typ.
• Digital signal input/output interface : 14-bit serial code in 2's complement format
• Transmission clock frequency
: 112 kHz min., 2048 kHz max.
• Filter characteristics
: Complies with ITU-T Recommendation G.714
• Built-in PLL eliminates a master clock
• Built-in PB tone signal generator
• Built-in service tone generator
• Built-in ringer tone generator
• General latch output: 1 bit
• Both transmit and receive gain adjustable by external control
• Receive interface: Speaker direct drive output
Earphone interface output : 600
W,
1 mW max.
Ringer output
: 70 nF, 4 V
PP
• Transmit gain adjustable using an external resistor
• Transmit microphone amplifier is eliminated by the gain setting of a maximum of 36 dB.
• Built-in reference voltage supply
• Serial 8-bit processor interface
• Package:
30-pin plastic SSOP (SSOP30-P-56-0.65-K) (Product name: MSM7728GS-K)
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¡ Semiconductor
MSM7728
BLOCK DIAGRAM
MAO
MAIN
–
+
SW1
VOL1
CODEC
RC
LPF
8th
BPF
14 BIT
ADCONV
AUTO
ZERO
BCLK
VOL2
5th
LPF
14 BIT
DACONV
RCONT
PCMOUT
TCONT
SYNC
SGC
SG
GEN
VR
GEN
SPK
PCMIN
RTIM
SPKP
–
+
PLL
SW 2
SW 4
SW CONTROL
LA
SPKN
–
+
VOL CONTROL
EAR
EAR
TOUT
LED
RINGP
RINGN
VOL4
RINGER
Tone
–
+
SW 3
SW 5
Tone GEN
VOL3
PB Tone
SERVICE Tone
POWER-DOWN
CONTROL
MCU
INF.
WRN
RDN
CDOUT
CDIN
DCLK
RSTN
SW 6
V
DD
AG
DG
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¡ Semiconductor
MSM7728
PIN CONFIGURATION (TOP VIEW)
SPKP
SPKN
EAR
RINGP
RINGN
TOUT
LED
LA
NC
1
2
3
4
5
6
7
8
9
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
AG
NC
NC
SGC
MAO
MAIN
NC
V
DD
NC
NC
RSTN
SYNC
BCLK
PCMOUT
PCMIN
RDN 10
CDOUT 11
WRN 12
DCLK 13
CDIN 14
DG 15
NC: No connection
30-Pin Plastic SSOP
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¡ Semiconductor
MSM7728
PIN AND FUNCTIONAL DESCRIPTIONS
V
DD
Power supply pin for 2.5 to 3.6 V (Typically 3.0 V).
AG
Analog signal ground.
DG
Ground pin for the digital signal circuits.
This ground is separated from the analog signal ground in this device. The DG pin must be
connected to the AG pin on the printed circuit board.
SGC
Bypass capacitor pin for generating the signal ground voltage level.
Insert a 0.1
mF
capacitor with excellent high frequency characteristics between the AG pin and
the SGC pin.
MAIN, MAO
Transmit microphone input and level adjustment.
MAIN is connected to the inverting input of the op-amp, and MAO is connected to the output
of the op-amp. This amplifier can set up a gain to a maximum of 36dB by using an external
resistor.
Level adjustment should be performed in a way below.
A transmit level of +6, 0, –6, or –12dB can be selected using control data from the processor
interface.
When CODEC is turned off, the MAO output goes high impedance.
C1
Microphone input
R1
R2
MAO
MAIN
–
+
R1 : variable
R2 > 20 kW
C1 > 1/(2
¥
3.14
¥
30
¥
R1) (F)
Gain = R2/R1 < 63
SG
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¡ Semiconductor
SPKP, SPKN
MSM7728
These pins are used for speaker driving.
The SPKN output is reversed in phase against the SPKP output when the gain is 1.
The receive output signal amplitude is 2.2V
PP
at maximum.
These outputs swing around the SG potential (signal ground potential, V
DD
/2) and can drive the
minimum 0.6kW load in pushpull driving mode.
The maximum output amplitude is 4.4V
PP
in pushpull driving mode (a load is inserted between
SPKN and SPKP).
Control data from the processor interface allows selecting the D/A conversion output, PB tone
output, or service tone output and also can provide a level control and mute control. When SPK
is turned off, the SG potential is output with high resistance.
EAR
Analog output for external accessary circuit.
This output swings around the SG potential and can drive the minimum 0.6kW against the SG
potential.
Control data from the processor interface allows selecting the D/A conversion output, PB tone
output, or service tone output and also can provide a level control and mute control. When EAR
is turned off, the SG potential is output with high resistance.
BCLK
Shift clock signal input for PCMIN and PCMOUT.
The frequency is equal to the data signaling rate.
SYNC
Synchronizing signal input.
In the transmit section, the PCM output signal from the PCMOUT pin is output synchronously
with this synchronizing signal. This synchronizing signal triggers the PLL and synchronizes all
timing signals of the transmit section.
In the receive section, 14 bits required are selected from serial input of PCM signals on the PCMIN
pin by the synchronizing signal.
Signals in the receive section are synchronized by this synchronizing signal. This signal must be
synchronized in phase with the BCLK.
When this signal frequency is 8 kHz, the transmit and receive paths have the frequency
characteristics specified by ITU-T G. 714. The frequency characteristics for 8 kHz are specified in
this data sheet.
For different frequencies of the SYNC signal, the frequency values in this data sheet should be
translated according to the following equation:
Frequency values described in the data sheet
¥
the SYNC frequency values to be actually used
8 kHz
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