E2U0017-28-81
¡ Semiconductor
MSM7578H/7578V/7579
¡ Semiconductor
Single Rail CODEC
This version: Aug. 1998
MSM7578H/7578V/7579
Previous version: Nov. 1996
GENERAL DESCRIPTION
The MSM7578 and MSM7579 are single-channel CODEC CMOS ICs for voice signals ranging
from 300 to 3400 Hz. These devices contain filters for A/D and D/A conversion.
Designed especially for a single-power supply and low-power applications, these devices are
particularly optimized for telephone terminals in digital wireless systems and ISDN systems.
The devices use the same transmission clocks as those used in the MSM7508B and MSM7509B.
The analog output signal can directly drive a piezoelectric type handset receiver.
FEATURES
• Single power supply: +5.0 V
±5%
• Low power consumption
Operating mode:
25 mW Typ. 47 mW Max. V
DD
= 5 V
Power down mode:
0.05 mW Typ. 0.3 mW Max. V
DD
= 5 V
• ITU-T Companding law
MSM7578H:
m-law
MSM7579:
A-law
MSM7578V:
m/A-law
pin-selectable
• Built-in PLL eliminates a master clock
• Serial data rate: 64/128/256/512/1024/2048 kHz
96/192/384/768/1536/1544/200 kHz
• Adjustable transmit gain
• Built-in reference voltage supply
• Directly drive a line transformer of 600
W
• The 16-pin DIP and 24-pin SOP package products provide pin compatibility with the MSM7508B/
7509B
• The 20-pin SSOP package products have 1/3 the foot print of conventional products
• Package options:
16-pin plastic DIP (DIP16-P-300-2.54)
(Product name : MSM7578HRS)
(Product name : MSM7579RS)
(Product name : MSM7578VRS)
24-pin plastic SOP (SOP24-P-430-1.27-K)
(Product name : MSM7578HGS-K)
(Product name : MSM7578VGS-K)
(Product name : MSM7579GS-K)
20-pin plastic SSOP (SSOP20-P-250-0.95-K) (Product name : MSM7578HMS-K)
(Product name : MSM7579MS-K)
(Product name : MSM7578VMS-K)
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¡ Semiconductor
MSM7578H/7578V/7579
BLOCK DIAGRAM
AIN–
AIN+
GSX
–
+
RC
LPF
8th
BPF
AD
CONV.
AUTO
ZERO
PCMOUT
TCONT
PLL
XSYNC
BCLK
SGC
SG
SG
GEN
VR
GEN
RTIM
RSYNC
(ALAW)
PCMIN
PDN
V
DD
AG
DG
AOUT
–
+
SG
5th
LPF
DA
CONV.
RCONT
PWD
Logic
PWD
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¡ Semiconductor
MSM7578H/7578V/7579
PIN CONFIGURATION (TOP VIEW)
SGC 1
SG 2
AOUT 3
V
DD
4
DG 5
PDN 6
RSYNC 7
PCMIN 8
16 AIN+
15 AIN–
14 GSX
13 (ALAW)*
12 AG
11 BCLK
10 XSYNC
9 PCMOUT
SGC 1
NC 2
SG 3
NC 4
AOUT 5
V
DD
6
DG 7
NC 8
NC 9
24 AIN+
23 AIN–
22 NC
21 GSX
20 NC
19 (ALAW)*
18 AG
17 NC
16 BCLK
15 NC
14 XSYNC
13 PCMOUT
SGC 1
SG 2
AOUT 3
V
DD
4
NC 5
NC 6
DG 7
PDN 8
RSYNC 9
PCMIN 10
20 AIN+
19 AIN–
18 GSX
17 (ALAW)*
16 NC
15 NC
14 AG
13 BCLK
12 XSYNC
11 PCMOUT
16-Pin Plastic DIP
PDN 10
RSYNC 11
PCMIN 12
NC : No connect pin
20-Pin Plastic SSOP
NC : No connect pin
24-Pin Plastic SOP
* The ALAW pin is only applied to the MSM7578VRS/MSM7578VGS-K/MSM7578VMS-K.
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¡ Semiconductor
MSM7578H/7578V/7579
PIN AND FUNCTIONAL DESCRIPTIONS
AIN+, AIN–, GSX
Transmit analog input and transmit level adjustment.
AIN+ is a non-inverting input to the op-amp; AIN– is an inverting input to the op-amp; GSX is
connected to the output of the op-amp and is used to adjust the level, as shown below.
When not using AIN– and AIN+, connect AIN– to GSX and AIN+ to SG. During power saving
and power down modes, the GSX output is at AG voltage.
1) Inverting input type
C1
Analog input
R1
GSX
AIN–
AIN+
SG
R1 : variable
R2 > 20 kW
C1 > 1/(2
¥
3.14
¥
30
¥
R1)
Gain = R2/R1
£
10
R2
–
+
2) Non inverting input type
C2
Analog input
R5
R4
R3
AIN+
AIN–
GSX
SG
+
–
R3 > 20 kW
R4 > 20 kW
R5 > 50 kW
C2 > 1/ (2
¥
3.14
¥
30
¥
R5)
Gain = 1 + R4 / R3
£
10
AG
Analog signal ground.
AOUT
Analog output.
The output signal has a maximum amplitude of 2.4 V
PP
above and below the signal ground
voltage (V
DD
/2).
The output load resistance is a minimum of 600
W.
During power saving, or power down mode, the output of AOUT is at the voltage level of the
signal ground.
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¡ Semiconductor
V
DD
Power supply for +5 V.
PCMIN
MSM7578H/7578V/7579
PCM signal input.
A serial PCM signal input to this pin is converted to an analog signal in synchronization with the
RSYNC signal and BCLK signal.
The data rate of the PCM signal is equal to the frequency of the BCLK signal.
The PCM signal is shifted at a falling edge of the BCLK signal and latched into the internal register
when shifted by eight bits.
The start of the PCM data (MSD) is identified at the rising edge of RSYNC.
BCLK
Shift clock signal input for the PCMIN and PCMOUT signal.
The frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, 2048,
or 200 kHz. Setting this signal to logic “1” or “0” drives both transmit and receive circuits to the
power saving state.
RSYNC
Receive synchronizing signal input.
Eight required bits are selected from serial PCM signals on the PCMIN pin by the receive
synchronizing signal.
Signals in the receive section are synchronized by this synchronizing signal. This signal must be
synchronized in phase with the BCLK. The frequency should be 8 kHz
±50
ppm to guarantee the
AC characteristics which are mainly the frequency characteristics of the receive section.
However, if the frequency characteristic of an applied system is not specified exactly, this device
can operate in the range of 8 kHz
±2
kHz, but the electrical characteristics in this specification are
not guaranteed.
XSYNC
Transmit synchronizing signal input.
The PCM output signal from the PCMOUT pin is output in synchronization with this transmit
synchronizing signal. This synchronizing signal triggers the PLL and synchronizes all timing
signals of the transmit section.
This synchronizing signal must be synchronized in phase with BCLK.
The frequency should be 8 kHz
±50
ppm to guarantee the AC characteristics which are mainly
the frequency characteristics of the transmit section.
However, if the frequency characteristic of an applied system is not specified exactly, this device
can operate in the range of 8 kHz
±2
kHz, but the electrical characteristics in this specification are
not guaranteed.
Setting this signal to logic “1” or “0” drives both transmit and receive circuits to the power saving
state.
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