SYMBOL
RD
WR
D0-D7
PIN
NO.
1
2
3-10
TYPE
I
I
I/O
ACTIVE
LEVEL
Low
Low
High
DESCRIPTION
READ: The RD input causes the 82C52 to output data to the data bus (D0-D7). data output
The
depends upon the state of the address inputs (A0-A1). CS0
enables the RDinput.
WRITE: The WRinput causes data from the data bus (D0-D7) to be input to 82C52. Addressing
the
and chip select action is the same as for read operations.
DATA BITS 0-7: The Data Bus provides eight, thre
e-state input/output lines for the transfer of data,
control and status information between the 82C52 and the CPU. character formats of less than 8
or F
bits, the corresponding D7, D6 and D5 are considered don t car data WRITE operations and
es for
are 0 for data READ operations. These lines are normally in igh impedance state except during
ah
read operations. D0 is the Least Significant Bit (LSB) and is first serial data bit to be received or
he t
transmitted.
ADDRESS INPUTS: The address lines select the rious internal registers during CPU bus
va
operations.
CRYSTAL/CLOCK: Crystal connections for the intern
al Baud Rate Generator. IX can also be used
as an external cloc input in ich case OX should be left open
wh
.
A0, A1
IX, OX
SDO
11, 12
13, 14
15
I
I/O
O
High
High
SERIAL DATA OUTPUT: Serial data output from the 82C52
transmitter circuitry. A Mar (1) is a logic
one (high) and Space (0) is logic zero (low). SD0 is held in th
e Mar condition when CTS false,
is
when RST is true, when the Transmitter Register is empty, or wh the Loop Mode.
en in
GROUND: Power supply ground connection.
CLEAR TO SEND: The logical state of the CTS is reflected in the CTS of the Modem Status
line
bit
Register. Any change of state in CTS
causes INTR to be set true when INTEN and MIEN are true. A
false level on CTSwill inhibit transmission of dat the SD0 output and willold SD0 in the Mar
a on
h
(high) state. If CTSgoes false during transmission, current character beingansmitted will be
the
tr
completed. CTSdoes not affect Loop Mode operation.
DATA SET READY: The logical state of the DSR is reflected in the Modem Status Register. Any
line
change of state of DSR
will cause INTR to be set if INTEN and MIEN are true. The stat this signal
e of
does not affect any other circuitry within the 82C52.
DATA TERMINAL READY: The DTR
signal can be set (low) by writing a logic 1 to the appropriat
e bit
in the Modem Control Register (MC This signal is cleared (hi by writing a logic 0 in the DTR
R).
gh)
bit
in the MCR or whenever a reset (RST
high) is applied to the 8
2C52.
REQUEST TO SEND: The RTS signal can be set (low) by wri a logic 1 to the appropriat in
ting
e bit
the MCR. This signal is cleared (h by writing a logic 0 to RTS bit in the MCR or whenever a
igh)
the
reset (RST
high) is applied to the 82C52.
CLOCK OUT: This output is user programmable to provideer a buffered IX output or a buffered
eith
Baud Rate Generator (16X) cloc output. The buffered IX (Crysta
l or external cloc source) output is
provided when the Baud Rate Select Register (BRSR) bit 7 is seta zero. Writing a logic one to
to
BRSR bit 7 causes the CO output to
provide a buffered versionf o internal Baud Rate Generator
the
cloc which operates at sixteen times the programmed baudOn reset D7 (CO select) is reset to
rate.
0.
GND
CTS
16
17
I
Low
Low
DSR
18
I
Low
DTR
19
O
Low
RTS
20
O
Low
CO
21
O
TBRE
22
O
High
TRANSMITTER BUFFER REGISTER EMPTY: The TBRE output is
set (high) whenever the
Transmitter Buffer Register (TBR) has transferred its datahe Transmit Register. Application of a
to t
reset (RST) to the 82C52 will also set the TBRE output. TBRE cleared (low) whenever data is
is
written to the TBR.
RESET: The RST input forces the 82C52 into an Idle m which all serial data activities are
ode in
suspended. The Modem Control Register (MCR) along with its asso outputs are cleared. The
ciated
UART Status Register (USR) is
cleared except for the TBRE andC bits, which are set. The 82C52
T
remains in an Idle state until programmed to resume serial da
ta activities. The RST input is a
Schmitt triggered input.
INTERRUPT REQUEST: The INTR output is enabled by the
INTEN bit in the Modem Control
Register (MCR). The MIEN bit selectively enables modem status c
hanges to provide an input to the
INTR logic. Figure 9 in Design Information shows the overall re
lationship of these interrupt control
signals.
RST
23
I
High
INTR
24
O
High
TABLE 2.
BAUD RATE
38.4K
19.2K
9600
7200
4800
3600
2400
2000†
†
DIVISOR
External
2
4
16/3
8
32/3
16
†
†
D7 D6 D5 D4 D3 D2 D1 D0
†
BAUD RATE
1800
2000
134.5
110
ACTUAL
1745.45
1986.2
133.33
109.09
PERCENT ERROR
3.03%
0.69%
0.87%
0.83%
Modem Control Register
The MCR is a general purpose control register which can be
written to and ead from. The RTSand DTR outputs are
r
directly controlled by their asso
ciated bits in this register.
Note that a logic one asserts true logic level (low) at these
a
output pins. The Interrupt Enable (INTEN) bit is the overall
control for the INTR output pin
. When INTEN is false, INTR
is held false (low).
FIGURE 2. BRSR
The Operating Mode
bits configure th 82C52 into one of
e
four possible modes. Normal
configures the 82C52 for
normal full or half duplex communications. Transmit Brea
enables the transmitter to onl
y transmit brea characters
(Start, Data and Stop bits all are logic zero). The Echo Mode
causes any data that is receiv on the SDI input pin to be
ed
retransmitted on the SDO output pin. Note that this output is
Analog electronics
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