SY89202U
Precision 1:8 LVPECL Fanout Buffer with
Three ÷1/÷2/÷4 Clock Divider Output Banks
General Description
The SY89202U is a precision, high-speed, integrated clock
divider LVPECL fanout buffer capable of handling clocks
up to 1.5GHz. Optimized for communications applications,
the three independently controlled output banks are phase
matched and can be configured for pass-through (÷1), ÷2
or ÷4 divide ratios.
The differential input includes Micrel’s unique, 3-pin input
termination architecture that allows the user to interface to
any AC- or DC-coupled signal as small as 100mV
(200mV
pp
) without any level shifting or termination resistor
networks in the signal path. The low skew, low jitter
outputs are 800mV, 100k compatible LVPECL, with
extremely fast rise/fall times guaranteed to be less than
220ps.
The EN (enable) input guarantees that the ÷1, ÷2 and ÷4
outputs will start from the same state without any runt
pulse after an asynchronous MR (master reset) is
asserted. This is accomplished by enabling the outputs
after a four-clock delay to allow the counters to
synchronize.
®
The SY89202U is part of Micrel’s Precision Edge product
family.
Datasheets and support documentation can be found on
Micrel’s web site at www.micrel.com.
Precision Edge
®
Features
•
•
Three low-skew LVPECL output banks with
programmable ÷1, ÷2 and ÷4 divider options
Three independently programmable output banks
Guaranteed AC performance over temp and voltage:
– >1.5GHz clock frequency (f
MAX
)
– <930ps In-to-Out t
pd
– <220ps t
r
/t
f
Ultra-low jitter design:
– <1ps
RMS
random jitter (RJ)
– <10ps
PP
total jitter (clock)
Internal input termination
Patent-pending input termination and VT pin accepts
AC- and DC-coupled inputs (CML, PECL, LVDS)
800mV LVPECL output swing
CMOS/TTL-compatible output enable (EN) and divider
select control
Power supply 2.5V +5% or 3.3V +10%
o
o
–40 C to +85 C industrial temperature range
Available in 32-pin QFN package
•
•
•
•
•
•
•
•
Applications
•
All SONET/SDH channel select applications
•
All Fibre Channel multi-channel select applications
•
All Gigabit Ethernet multi-channel select applications
Markets
•
•
•
•
LAN/WAN
Enterprise servers
ATE
Test and measurement
United States Patent No. RE44,134
Precision Edge is a registered trademark of Micrel, Inc
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (
408
) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
August 2007
M9999-083107-C
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY89202U
Functional Block Diagram
August 2007
2
M9999-083107-C
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY89202U
Ordering Information
Part Number
SY89202UMG
SY89202UMGTR
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A
= 25_C, DC Electricals Only.
2. Tape and Reel.
(2)
Package Type
QFN-32
QFN-32
Operating
Range
Industrial
Industrial
Package Marking
SY89202U with Pb-Free
bar-line indicator
SY89202U with Pb-Free
bar-line indicator
Lead Finish
NiPdAu
Pb-Free
NiPdAu
Pb-Free
Pin Configuration
32-Pin QFN
August 2007
3
M9999-083107-C
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY89202U
Pin Description
Pin Number
2, 7, 8
Pin Name
DIVSEL1
DIVSEL2
DIVSEL3
IN, /IN
Pin Function
Single-Ended Inputs: These TTL/CMOS inputs select the divide ratio for each of the three
banks of outputs. Note that each of these inputs is internally connected to a 25k
Ω pull
up
-
resistor and will default to logic HIGH state if left open. The input-switching threshold is V
CC
/2.
Differential Input: This input pair is the differential signal input to the device. This input accepts
AC- or DC-coupled signals as small as 100mV. The input pair internally terminates to a VT pin
through 50Ω.
Note that these inputs will default to an indeterminate state if left open. Please
refer to the “Input Interface Applications” section for more details.
Input Termination Center-Tap: Each side of the differential input pair terminates to the VT pin.
The VT pin provides a center-tap to a termination network for maximum interface flexibility.
See “Input Interface Applications” section for more details.
Reference Voltage: This output biases to V
CC
–1.2V. It is used for AC-coupling inputs IN and
/IN. For AC-coupled applications, connect V
REF-AC
directly to the VT pin. Bypass with 0.01µF
low ESR capacitor to V
CC
.
Single-Ended Input: This TTL/CMOS input disables and enables the Q0 – Q7 outputs. This
input is internally connected to a 25kΩ
pull-up
resistor and will default to logic HIGH state if left
open. The input-switching threshold is V
CC
/2. For the input enable and disable functional
description, refer to “Timing Diagram” section.
Positive power supply. Bypass with 0.1µF||0.01µF low ESR capacitors as close to VCC pins
as possible.
Bank 2 LVPECL differential output pairs controlled by DIVSEL2: LOW, Q4 – Q6 = ÷2, HIGH,
Q4 – Q6 = ÷4. Unused output pairs may be left open. Each output is designed to drive 800mV
into 50Ω
terminated at V
CC
–2V.
Bank 1 LVPECL differential output pairs controlled by DIVSEL1: LOW, Q0 – Q3 = ÷1, HIGH,
Q0 – Q3 = ÷2. Unused output pairs may be left open. Each output is designed to drive 800mV
into 50Ω
terminated at V
CC
–2V.
Bank 3 LVPECL differential output pair controlled by DIVSEL3: LOW, Q7 = ÷2, HIGH, Q7 =
÷4. Unused output pairs may be left open. Each output is designed to drive 800mV into 50
Ω
terminated at V
CC
–2V.
Single-Ended Input: This TTL/CMOS-compatible master reset function asynchronously sets
Q0 – Q7 outputs LOW and /Q0 – /Q7 outputs HIGH, and holds them in that state as long as
the /MR input remains LOW. This input is internally connected to a 25k
Ω pull
up resistor and
-
will default to a logic HIGH state if left open. The input-switching threshold is V
CC
/2.
Ground: Ground pin and exposed pad must be connected to the same ground plane.
3, 6
4
VT
5
VREF-AC
9
EN
10, 19, 22, 31
16, 15, 14,
13, 12, 11
30, 29, 28,
27, 26, 25,
24, 23
18, 17
VCC
Q4, /Q4, Q5,
/Q5, Q6, /Q6
Q0, /Q0, Q1,
/Q1, Q2, /Q2,
Q3, /Q3
Q7, /Q7
32
/MR
GND,
Exposed Pad
1, 20, 21
Truth Table
/MR
0
1
1
1
Notes:
1. /MR asynchronously forces Q0 – Q7 LOW (/Q0 - /Q7 HIGH).
2. EN forces Q0 – Q7 LOW between 2 and 6 input clock cycles after the falling edge of EN. Refer to “Timing Diagram” section.
3. EN synchronously enables the outputs between 2 and 6 input clock cycles after the rising edge of EN. Refer to “Timing Diagram” section.
( 1)
EN
( 2, 3)
DIVSEL1
X
X
0
1
DIVSEL2
X
X
0
1
DIVSEL3
X
X
0
1
Q0 – Q3
0
0
˜1
˜2
Q4 – Q6
0
0
˜2
˜4
Q7
0
0
˜2
˜4
X
0
1
1
August 2007
4
M9999-083107-C
hbwhelp@micrel.com
or (408) 955-1690
Micrel, Inc.
SY89202U
Absolute Maximum Ratings
(1)
Supply Voltage (V
CC
) .......................... –0.5V to +4.0V
Input Voltage (V
IN
) .................................. –0.5V to V
CC
Termination Current
Source or sink current on V
T
................... ±100mA
Output Current
Source or sink current on IN, /IN .............. ±50mA
V
REF-AC
Current
Source or sink current on V
REF-AC
............ ±1.5mA
Lead Temperature (soldering, 20 sec.) .......... +260ºC
Storage Temperature (T
s
) ................. –65ºC to 150ºC
Operating Ratings
(2)
Supply Voltage (V
CC
) .................. +2.375V to +2.625V
..................................................... +3.0V to +3.6V
Ambient Temperature (T
A
) ................ –40ºC to +85ºC
(3)
Package Thermal Resistance
QFN (θ
JA
)
Still-Air ..................................................... 35ºC/W
QFN (ψ
JB
)
Junction-to-Board .................................... 20ºC/W
DC Electrical Characteristics
(4)
T
A
=–40°C to +85°C, unless noted.
Symbol
V
CC
I
CC
R
DIFF_IN
R
IN
V
IH
V
IL
V
IN
V
DIFF_IN
V
REF-AC
IN-to-V
T
Notes:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied
at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended
periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Package Thermal Resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB.
θ
JA
and
ψ
JB
values are determined for a 4-layer board in still air, unless otherwise stated.
4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Parameter
Power Supply
Power Supply Current
Differential Input Resistance
(IN-to-/IN)
Input Resistance
(IN-to-V
T
)
Input High Voltage
(IN, /IN)
Input Low Voltage
(IN, /IN)
Input Voltage Swing
(IN, /IN)
Differential Input Voltage Swing
|IN-/IN|
Output Reference Voltage
(V
REF-AC
)
Voltage from Input to V
T
Condition
Min
2.375
3.0
Typ
Max
2.625
3.6
Units
V
V
mA
Ω
Ω
V
V
V
V
No load, max. V
CC
90
45
1.2
0
See Figure 1a.
See Figure 1b.
0.1
0.2
V
CC
–1.3
125
100
50
180
110
55
V
CC
V
IH
–0.1
V
CC
V
CC
–1.2
V
CC
–1.1
1.8
V
V
August 2007
5
M9999-083107-C
hbwhelp@micrel.com
or (408) 955-1690
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