DS1010
10-Tap Silicon Delay Line
www.dalsemi.com
FEATURES
All-silicon time delay
10 taps equally spaced
Delays are stable and precise
Leading and trailing edge accuracy
Delay tolerance ±5% or ±2 ns, whichever is
greater
Economical
Auto-insertable, low profile
Standard 14-pin DIP or 16-pin SOIC
Low-power CMOS
TTL/CMOS-compatible
Vapor phase, IR and wave solderable
Custom delays available
Fast turn prototypes
IN1
NC
TAP 2
TAP 4
TAP 6
TAP 8
GND
PIN ASSIGNMENT
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
TAP 1
IN1
TAP 3
TAP 5
TAP 7
TAP 9
TAP 10
NC
NC
TAP 2
TAP 4
TAP 6
TAP 8
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
NC
TAP 1
TAP 3
TAP 5
TAP 7
TAP 9
TAP 10
DS1010 14-Pin DIP (300-mil)
See Mech. Drawings Section
DS1010S 16-Pin SOIC
(300-mil)
See Mech. Drawings Section
PIN DESCRIPTION
TAP 1 - TAP 10
V
CC
GND
NC
IN
- TAP Output Number
- 5 Volts
- Ground
- No Connection
- Input
DESCRIPTION
The DS1010 series delay line has ten equally spaced taps providing delays from 5 ns to 500 ns. The
devices are offered in a standard 14-pin DIP which is pin-compatible with hybrid delay lines.
Alternatively, a 16-pin SOIC is available for surface mount technology which reduces PC board area.
Since the DS1010 is an all-silicon solution, better economy is achieved when compared to older methods
using hybrid techniques. The DS1010 series delay lines provide a nominal accuracy of ±5% or ±2 ns,
whichever is greater. The DS1010 reproduces the input logic state at the TAP 10 output after a fixed
delay as specified by the dash number extension of the part number. The DS1010 is designed to produce
both leading and trailing edge with equal precision. Each tap is capable of driving up to 10 74LS type
loads. Dallas Semiconductor can customize standard products to meet special needs. For special requests
and rapid delivery, call (972) 371-4348.
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111799
DS1010
LOGIC DIAGRAM
Figure 1
PART NUMBER DELAY TABLE (t
PHL
, t
PLH
)
Table 1
CATALOG P/N
DS1010-50
DS1010-60
DS1010-75
DS1010-80
DS1010-100
DS1010-125
DS1010-150
DS1010-175
DS1010-200
DS1010-250
DS1010-300
DS1010-350
DS1010-400
DS1010-450
DS1010-500
Custom delays available.
TOTAL DELAY
50
60
75
80
100
125
150
175
200
250
300
350
400
450
500
DELAY/TAP (ns)
5
6
7.5
8
10
12.5
15
17.5
20
25
30
35
40
45
50
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DS1010
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature
Storage Temperature
Soldering Temperature
Short Circuit Output Current
-1.0V to +7.0V
0°C to 70°C
-55°C to +125°C
260°C for 10 seconds
50 mA for 1 second
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
DC ELECTRICAL CHARACTERISTICS
PARAMETER
Supply Voltage
High Level Input
Voltage
Low Level Input
Voltage
Input Leakage
Current
Active Current
High Level Output
Current
Low Level Output
Current
SYM
V
CC
V
IH
V
IL
I
I
I
CC
I
OH
I
OL
0.0V
≤
V
I
≤
V
CC
V
CC
=Max;
Period=Min.
V
CC
=Min.
V
OH
=4
V
CC
=Min.
V
OL
=0.5
TEST
CONDITION
MIN
4.75
2.2
-0.5
-1.0
(0°C to 70°C; V
CC
= 5.0V ± 5%)
TYP
5.00
MAX
5.25
V
CC
+ 0.5
0.8
1.0
40
150
-1.0
12
UNITS
V
V
V
µA
mA
mA
mA
2
NOTES
1
1
1
AC ELECTRICAL CHARACTERISTICS
PARAMETER
Input Pulse Width
Input to Tap Delay
(leading edge)
Input to Tap Delay
(trailing edge)
Power-up Time
SYMBOL
t
WI
t
PLH
t
PHL
t
PU
Period
MIN
40% of TAP 10 t
PLH
(T
A
= 25°C; V
CC
= 5V ± 5%)
TYP
Table 1
Table 1
100
MAX
UNITS
ns
ns
ns
ms
ns
NOTES
8
3, 4, 5, 6,
7, 9
3, 4, 5, 6,
7, 9
8
4 (t
WI
)
CAPACITANCE
PARAMETER
Input Capacitance
SYMBOL
C
IN
MIN
TYP
5
MAX
10
(T
A
= 25°C)
UNITS
pF
NOTES
3 of 6
DS1010
NOTES:
1. All voltages are referenced to ground.
2. Measured with outputs open.
3. V
CC
= 5V @ 25°C. Input-to-tap delays accurate on both rising and falling edges within ±2 ns or ±5%
whichever is greater.
4. See “Test Conditions” section.
5. For DS1010 delay lines with a TAP 10 delay of 100 ns or greater, temperature variations from 25°C
to 0°C or 70°C may produce an additional input-to-tap delay shift of
±2ns
or
±3%,
whichever is
greater.
6. For DS1010 delay lines with a TAP 10 delay less than 100 ns, temperature variations from 25°C to
0°C or 70°C may produce an additional input-to-tap delay shift of
±1
ns or
±9%,
whichever is greater.
7. All tap delays tend to vary unidirectionally with temperature or voltage changes. For example, if TAP
1 slows down, all other taps will also slow down; TAP 3 can never be faster than TAP 2.
8. Pulse width and period specifications may be exceeded; however, accuracy will be application-
sensitive (decoupling, layout, etc.).
9. Certain high-frequency applications not recommended for -50 in 16-pin package. Consult factory.
TIMING DIAGRAM: SILICON DELAY LINE
Figure 2
4 of 6
DS1010
TEST CIRCUIT
Figure 3
TERMINOLOGY
Period:
The time elapsed between the leading edge of the first pulse and the leading edge of the
following pulse.
t
WI
(Pulse Width):
The elapsed time on the pulse between the 1.5V point on the leading edge and the
1.5V point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V point on the leading
edge.
t
RISE
(Input Rise Time):
The elapsed time between the 20% and the 80% point on the leading edge of the
input pulse.
t
FALL
(Input Fall Time):
The elapsed time between the 80% and the 20% point on the trailing edge of the
input pulse.
t
PLH
(Time Delay Rising):
The elapsed time between the 1.5V point on the leading edge of the input
pulse and the 1.5V point on the leading edge of any tap output pulse.
t
PHL
(Time Delay, Falling):
The elapsed time between the 1.5V point on the trailing edge of the input
pulse and the 1.5V point on the trailing edge of any tap output pulse.
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