MC14516B
Binary Up/Down Counter
The MC14516B synchronous up/down binary counter is
constructed with MOS P−channel and N−channel enhancement mode
devices in a monolithic structure.
This counter can be preset by applying the desired value, in binary,
to the Preset inputs (P0, P1, P2, P3) and then bringing the Preset
Enable (PE) high. The direction of counting is controlled by applying
a high (for up counting) or a low (for down counting) to the
UP/DOWN input. The state of the counter changes on the positive
transition of the clock input.
Cascading can be accomplished by connecting the Carry Out to the
Carry In of the next stage while clocking each counter in parallel. The
outputs (Q0, Q1, Q2, Q3) can be reset to a low state by applying a high
to the reset (R) pin.
This CMOS counter finds primary use in up/down and difference
counting. Other applications include: (1) Frequency synthesizer
applications where low power dissipation and/or high noise immunity
is desired, (2) Analog−to−Digital and Digital−to−Analog conversions,
and (3) Magnitude and sign generation.
Features
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MARKING
DIAGRAMS
PDIP−16
P SUFFIX
CASE 648
1
SOIC−16
D SUFFIX
CASE 751B
1
16
14516BG
AWLYWW
1
16
MC14516BCP
AWLYYWWG
1
•
•
•
•
•
•
•
•
•
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Internally Synchronous for High Speed
Logic Edge−Clocked Design — Count Occurs on Positive Going
Edge of Clock
Single Pin Reset
Asynchronous Preset Enable Operation
Capable of Driving Two Low−Power TTL Loads or One
Low−Power Schottky Load Over the Rated Temperature Range
These Devices are Pb−Free and are RoHS Compliant
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
SOEIAJ−16
F SUFFIX
CASE 966
1
A
WL, L
YY, Y
WW, W
G
16
MC14516B
ALYWG
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
MAXIMUM RATINGS
(Voltages Referenced to V
SS
)
Parameter
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Input or Output Current (DC or Transient)
per Pin
Power Dissipation, per Package (Note 1)
Ambient Temperature Range
Storage Temperature Range
Lead Temperature (8−Second Soldering)
Symbol
V
DD
V
in
, V
out
I
in
, I
out
P
D
T
A
T
stg
T
L
Value
−0.5
to +18.0
−0.5
to V
DD
+ 0.5
±
10
500
−55
to +125
−65
to +150
260
Unit
V
V
mA
mW
°C
°C
°C
This device contains protection circuitry to guard
against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated
voltages to this high−impedance circuit. For proper
operation, V
in
and V
out
should be constrained to the
range V
SS
v
(V
in
or V
out
)
v
V
DD
.
Unused inputs must always be tied to an appropriate
logic voltage level (e.g., either V
SS
or V
DD
). Unused
outputs must be left open.
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating: Plastic “P and D/DW”
Packages: – 7.0 mW/_C From 65_C To 125_C
©
Semiconductor Components Industries, LLC, 2013
May, 2013
−
Rev. 9
1
Publication Order Number:
MC14516B/D
MC14516B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS
(Voltages Referenced to V
SS
)
−
55_C
V
DD
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
5.0
10
15
5.0
10
15
15
−
5.0
10
15
5.0
10
15
25_C
125_C
Characteristic
Symbol
V
OL
Vdc
Min
−
−
−
4.95
9.95
14.95
−
−
−
3.5
7.0
11
– 3.0
– 0.64
– 1.6
– 4.2
0.64
1.6
4.2
−
−
−
−
−
Max
Min
−
−
−
4.95
9.95
14.95
−
−
−
3.5
7.0
11
– 2.4
– 0.51
– 1.3
– 3.4
0.51
1.3
3.4
−
−
−
−
−
Typ
(Note 2)
0
0
0
5.0
10
15
2.25
4.50
6.75
2.75
5.50
8.25
– 4.2
– 0.88
– 2.25
– 8.8
0.88
2.25
8.8
±
0.00001
5.0
0.005
0.010
0.015
Max
Min
−
−
−
4.95
9.95
14.95
−
−
−
3.5
7.0
11
– 1.7
– 0.36
– 0.9
– 2.4
0.36
0.9
2.4
−
−
−
−
−
Max
Unit
Vdc
Output Voltage
V
in
= V
DD
or 0
V
in
= 0 or V
DD
“0” Level
“1” Level
0.05
0.05
0.05
−
−
−
1.5
3.0
4.0
−
−
−
−
−
−
−
−
−
−
±
0.1
−
5.0
10
20
0.05
0.05
0.05
−
−
−
1.5
3.0
4.0
−
−
−
−
−
−
−
−
−
−
±
0.1
7.5
5.0
10
20
0.05
0.05
0.05
−
−
−
1.5
3.0
4.0
−
−
−
−
−
−
−
−
−
−
±
1.0
−
150
300
600
V
OH
Vdc
Input Voltage
“0” Level
(V
O
= 4.5 or 0.5 Vdc)
(V
O
= 9.0 or 1.0 Vdc)
(V
O
= 13.5 or 1.5 Vdc)
“1” Level
(V
O
= 0.5 or 4.5 Vdc)
(V
O
= 1.0 or 9.0 Vdc)
(V
O
= 1.5 or 13.5 Vdc)
Output Drive Current
(V
OH
= 2.5 Vdc)
(V
OH
= 4.6 Vdc)
(V
OH
= 9.5 Vdc)
(V
OH
= 13.5 Vdc)
(V
OL
= 0.4 Vdc)
(V
OL
= 0.5 Vdc)
(V
OL
= 1.5 Vdc)
Input Current
Input Capacitance (V
in
= 0)
Quiescent Current (Per Package)
Source
V
IL
Vdc
V
IH
Vdc
I
OH
mAdc
Sink
I
OL
mAdc
I
in
C
in
I
DD
mAdc
pF
mAdc
Total Supply Current (Note 3, 4)
(Dynamic plus Quiescent,
Per Package)
(C
L
= 50 pF on all outputs, all
buffers switching)
I
T
I
T
= (0.58
mA/kHz)
f + I
DD
I
T
= (1.20
mA/kHz)
f + I
DD
I
T
= (1.70
mA/kHz)
f + I
DD
mAdc
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF: I
T
(C
L
) = I
T
(50 pF) + (C
L
– 50) Vfk where: I
T
is in
mA
(per package), C
L
in pF,
V = (V
DD
– V
SS
) in volts, f in kHz is input frequency, and k = 0.001.
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3
MC14516B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS
(Note 5) (C
L
= 50 pF, T
A
= 25_C)
Characteristic
All Types
Symbol
t
TLH
,
t
THL
V
DD
5.0
10
15
Min
−
−
−
Typ
(Note 6)
100
50
40
Max
200
100
80
Unit
ns
Output Rise and Fall Time
t
TLH
, t
THL
= (1.5 ns/pF) C
L
+ 25 ns
t
TLH
, t
THL
= (0.75 ns/pF) C
L
+ 12.5 ns
t
TLH
, t
THL
= (0.55 ns/pF) C
L
+ 9.5 ns
Propagation Delay Time
Clock to Q
t
PLH
, t
PHL
= (1.7 ns/pF) C
L
+ 230 ns
t
PLH
, t
PHL
= (0.66 ns/pF) C
L
+ 97 ns
t
PLH
, t
PHL
= (0.5 ns/pF) C
L
+ 75 ns
Clock to Carry Out
t
PLH
, t
PHL
= (1.7 ns/pF) C
L
+ 230 ns
t
PLH
, t
PHL
= (0.66 ns/pF) C
L
+ 97 ns
t
PLH
, t
PHL
= (0.5 ns/pF) C
L
+ 75 ns
Carry In to Carry Out
t
PLH
, t
PHL
= (1.7 ns/pF) C
L
+ 230 ns
t
PLH
, t
PHL
= (0.66 ns/pF) C
L
+ 97 ns
t
PLH
, t
PHL
= (0.5 ns/pF) C
L
+ 75 ns
Preset or Reset to Q
t
PLH
, t
PHL
= (1.7 ns/pF) C
L
+ 230 ns
t
PLH
, t
PHL
= (0.66 ns/pF) C
L
+ 97 ns
t
PLH
, t
PHL
= (0.5 ns/pF) C
L
+ 75 ns
Preset or Reset to Carry Out
t
PLH
, t
PHL
= (1.7 ns/pF) C
L
+ 465 ns
t
PLH
, t
PHL
= (0.66 ns/pF) C
L
+ 192 ns
t
PLH
, t
PHL
= (0.5 ns/pF) C
L
+ 125 ns
Reset Pulse Width
t
PLH
,
t
PHL
ns
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
380
200
160
350
170
140
−
−
−
650
230
180
−
−
−
260
120
100
0
20
20
500
200
150
– 70
– 10
0
– 40
– 30
– 25
480
420
420
200
100
80
315
130
100
315
130
100
180
80
60
315
130
100
550
225
150
190
100
80
200
100
75
3.0
6.0
8.0
325
115
90
−
−
−
130
60
50
– 60
– 20
0
250
100
75
– 160
– 60
– 40
– 120
– 70
– 50
240
210
210
100
50
40
630
260
200
630
260
200
360
160
120
630
360
200
1100
450
300
−
−
−
−
−
−
1.5
3.0
4.0
−
−
15
5
4
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
ms
ns
ns
t
PLH
,
t
PHL
t
PLH
,
t
PHL
ns
t
PLH
,
t
PHL
ns
t
PLH
,
t
PHL
ns
t
w
t
WH
f
cl
t
rem
t
TLH
,
t
THL
t
su
t
h
t
su
t
h
t
su
t
h
t
WH
ns
Clock Pulse Width
ns
Clock Pulse Frequency
MHz
Preset or Reset Removal Time
The Preset or Reset signal must be low prior to a
positive−going transition of the clock.
Clock Rise and Fall Time
ns
Setup Time
Carry In to Clock
Hold Time
Clock to Carry In
Setup Time
Up/Down to Clock
Hold Time
Clock to Up/Down
Setup Time
Pn to PE
Hold Time
PE to Pn
Preset Enable Pulse Width
ns
ns
ns
ns
ns
ns
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an Indication of the IC’s potential performance.
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