19-6075; Rev 11/11
SmartWatch RAM (DS1216B/C/D/H);
SmartWatch ROM (DS1216E/F)
GENERAL DESCRIPTION
The DS1216 SmartWatch RAM and SmartWatch
ROM sockets are 600-mil-wide DIP sockets with a
built-in CMOS watch function, an NV RAM
controller circuit, and an embedded lithium energy
source. The sockets provide an NV RAM solution
for memory sized from 2K x 8 to 512K x 8 with
package sizes from 26 pins to 32 pins. When a
socket is mated with a CMOS SRAM, it provides a
complete solution to problems associated with
memory volatility and uses a common energy
source to maintain time and date. The SmartWatch
ROM sockets use the embedded lithium source to
maintain the time and date only. A key feature of
the SmartWatch is that the watch function remains
transparent to the RAM. The SmartWatch monitors
V
CC
for an out-of-tolerance condition. When such a
condition occurs, an internal lithium energy source
is automatically switched on and write protection
is unconditionally enabled to prevent loss of watch
and RAM data.
DS1216
FEATURES
Keeps Track of Hundredths of Seconds,
Seconds, Minutes, Hours, Days, Date of the
Month, Months, and Years
Converts Standard 2K x 8 Up to 512K x 8
CMOS Static RAMs into Nonvolatile Memory
Embedded Lithium Energy Cell Maintains
Watch Information and Retains RAM Data
Watch Function is Transparent to RAM
Operation
Automatic Leap Year Compensation Valid Up
to 2100
Lithium Energy Source is Electrically
Disconnected to Retain Freshness Until Power
is Applied for the First Time
Proven Gas-Tight Socket Contacts
Full
±10%
Operating Range
Accuracy Better Than
±1
Minute/Month
at +25°C
TYPICAL OPERATING CIRCUIT
ORDERING INFORMATION
PART
DS1216B
DS1216C
DS1216D
DS1216E
DS1216F
DS1216H
TEMP RANGE
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
PIN-PACKAGE
28 SmartWatch Socket
28 SmartWatch Socket
32 SmartWatch Socket
28 SmartWatch Socket
32 SmartWatch Socket
32 SmartWatch Socket
(See Figure 2 for letter suffix marking identification.)
Selector Guide appears on page 2.
1 of 15
DS1216 SmartWatch RAM/SmartWatch ROM
PIN DESCRIPTION
RST
DQ0
A2
A0
GND
CE
- Reset, Active Low
- Data Input/Output 0 (RAM)
- Address Bit 2 (Read/Write [ROM])
- Address Bit 0 (Data Input [ROM])
- Ground
- Conditioned Chip Enable, Active Low
OE
WE
V
CC
V
CC
B
V
CC
D
- Output Enable, Active Low
- Write Enable, Active Low
- Switched V
CC
for 28-/32-Pin RAM
- Switched V
CC
for 24-Pin RAM
- Switched V
CC
for 28-Pin RAM
PIN CONFIGURATIONS
TOP VIEW
RST
1
2
3
4
5
6
7
[A2] 8
9
[A0] 10
DQ0 11
12
13
GND 14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CE
OE
V
CC
WE
V
CC
B
1
2
3
4
5
6
7
8
9
[A2] 10
11
[A0] 12
DQ0 13
14
15
GND 16
RST
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
V
CC
D
WE
OE
CE
DS1216B/C/E
28-Pin Intelligent Socket
DS1216D/F/H
32-Pin Intelligent Socket
SELECTOR GUIDE
PART
DS1216B
DS1216C
DS1216D
DS1216E
DS1216F
DS1216H
RAM/ROM
RAM
RAM
RAM
ROM
ROM
RAM
RAM DENSITY
16K/64K
64K/256K
256K/1M
64K/256K
64K/256K/1M
1M/4M
PC BOARD MODIFICATION
REQUIRED FOR DENSITY
UPGRADE?
No/Yes
No
No/Yes
No
No
No
2 of 15
DS1216 SmartWatch RAM/SmartWatch ROM
DETAILED DESCRIPTION
The DS1216 SmartWatch RAM and SmartWatch ROM Sockets are 600-mil-wide DIP sockets with a
built-in CMOS watch function, an NV RAM controller circuit, and an embedded lithium energy source.
The sockets provide an NV RAM solution for memory sized from 2K x 8 to 512K x 8 with package sizes
from 26 pins to 32 pins. When a socket is mated with a CMOS SRAM, it provides a complete solution to
problems associated with memory volatility and uses a common energy source to maintain time and date.
The SmartWatch ROM sockets use the embedded lithium source to maintain the time and date only. A
key feature of the SmartWatch is that the watch function remains transparent to the RAM. The
SmartWatch monitors V
CC
for an out-of-tolerance condition. When such a condition occurs, an internal
lithium energy source is automatically switched on and write protection is unconditionally enabled to
prevent loss of watch and RAM data.
Using the SmartWatch saves PC board space since the combination of SmartWatch and the mated RAM
take up no more area than the memory alone. The SmartWatch uses the V
CC
, data I/O 0,
CE, OE,
and
WE
for RAM and watch control. All other pins are passed straight through to the socket receptacle.
The SmartWatch provides timekeeping information including hundredths of seconds, seconds, minutes,
hours, days, date, months, and years. The date at the end of the month is automatically adjusted for
months with fewer than 31 days, including correction for leap years. The SmartWatch operates in either
24-hour or 12-hour format with an AM/PM indicator.
OPERATION
Communication with the SmartWatch RAM is established by pattern recognition on a serial bit stream of
64 bits that must be matched by executing 64 consecutive write cycles containing the proper data on
DQ0. On the SmartWatch ROM, communication with the clock is established using A2 and A0, and
either
OE
or
CE.
All accesses that occur prior to recognition of the 64-bit pattern are directed to memory.
After the pattern match, the next 64 reads and/or writes are directed to the clock, and the RAM is
disabled. Once the pattern is established, the next 64 read/write cycles will be directed to the RTC
registers. When power is cycled, 64 reads should be executed prior to any writes to ensure that the RTC
registers are not written. A pattern match is ignored if the
RST
bit is zero and the
RST
pin goes low
during the match sequence. A pattern match is also terminated if a read occurs during the 64-bit match
sequence.
PATTERN MATCH—RAM
Data transfer to and from the timekeeping registers is accomplished with a serial bit stream under control
of chip enable (CE), output enable (OE), and write enable (WE). Initially, a read cycle to any memory
location using the
CE
and
OE
control of the SmartWatch starts the pattern recognition sequence by
moving a pointer to the first bit of the 64-bit comparison register. Next, 64 consecutive write cycles are
executed using the
CE
and
WE
control of the SmartWatch. These 64 write cycles are used only to gain
access to the SmartWatch. Therefore, any address to the memory in the socket is acceptable. However,
the write cycles generated to gain access to the SmartWatch are also writing data to a location in the
mated RAM. The preferred way to manage this requirement is to set aside just one address location in
RAM as a SmartWatch scratch pad. When the first write cycle is executed, it is compared to bit 0 of the
64-bit comparison register. If a match is found, the pointer increments to the next location of the
3 of 15
DS1216 SmartWatch RAM/SmartWatch ROM
comparison register and awaits the next write cycle. If a match is not found, the pointer does not advance
and all subsequent write cycles are ignored. If a read cycle occurs at any time during pattern recognition,
the present sequence is aborted and the comparison register pointer is reset. Pattern recognition continues
for 64 write cycles as described above until all the bits in the comparison register have been matched (this
bit pattern is shown in Figure 1). With a correct match for 64 bits, the SmartWatch is enabled and data
transfer to or from the timekeeping registers can proceed. The next 64 cycles will cause the SmartWatch
to either receive or transmit data on DQ0, depending on the level of the
OE
pin or the
WE
pin. Cycles to
other locations outside the memory block can be interleaved with
CE
cycles without interrupting the
pattern recognition sequence or data transfer sequence to the SmartWatch.
PATTERN MATCH—ROM
Communication with the SmartWatch is established by pattern recognition of a serial bit stream of 64 bits
that must be matched by executing 64 consecutive write cycles, placing address bit A2 low with the
proper data on address bit A0. The 64 write cycles are used only to gain access to the SmartWatch. Prior
to executing the first of 64 write cycles, a read cycle should be executed by holding A2 high. The read
cycle will reset the comparison register pointer within the SmartWatch, ensuring the pattern recognition
starts with the first bit of the sequence. When the first write cycle is executed, it is compared to bit 0 of
the 64-bit comparison register. If a match is found, the pointer increments to the next location of the
comparison register and awaits the next write cycle. If a match is not found, the pointer does not advance
and all subsequent write cycles are ignored. If a read cycle occurs at any time during pattern recognition,
the present sequence is aborted and the comparison register pointer is reset. Pattern recognition continues
for a total of 64 write cycles as described above, until all the bits in the comparison register have been
matched (this bit pattern is shown in Figure 1). With a correct match for 64 bits, the SmartWatch is
enabled and data transfer to or from the timekeeping registers can proceed. The next 64 cycles will cause
the SmartWatch to either receive data on data in (A0) or transmit data on data out (DQ0), depending on
the level of /WRITE READ (A2).
After power-up, the controller could be in the 64-bit clock register read/write sequence (from an
incomplete access prior to power-down). Therefore, it is recommended that a 64-bit read be performed
upon power-up to prevent accidental writes to the clock, and to prevent reading clock data when access to
the RAM would otherwise be expected.
4 of 15
DS1216 SmartWatch RAM/SmartWatch ROM
Figure 1. SmartWatch Comparison Register Definition
7
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
HEX
VALUE
C5
3A
A3
5C
C5
3A
A3
5C
BYTE 0
BYTE 1
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTE 6
BYTE 7
1
0
0
1
1
0
0
1
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
0
1
1
0
0
1
1
0
NOTE:
THE PATTERN RECOGNITION IN HEX IS C5, 3A, 5C, C5, 3A, A3, 5C. THE ODDS OF THIS PATTERN
ACCIDENTALLY DUPLICATING AND CAUSING INADVERTENT ENTRY TO THE SMARTWATCH ARE LESS
THAN 1 IN 10
19
. THIS PATTERN IS SENT TO THE SMARTWATCH LSB TO MSB.
The DS1216 SmartWatch performs circuit functions required to make a CMOS RAM nonvolatile. First, a
switch is provided to direct power from the battery or V
CC
supply, depending on which voltage is greater.
This switch has a voltage drop of less than 0.2V. The second function that the SmartWatch provides is
power-fail detection, which occurs at V
TP
. The DS1216 constantly monitors the V
CC
supply. When V
CC
goes out of tolerance, a comparator outputs a power-fail signal to the chip-enable logic. The third function
accomplishes write protection by holding the chip-enable signal to the memory within 0.2V of V
CC
or
battery. During nominal power-supply conditions, the memory chip-enable signal will track the chip-
enable signal sent to the socket with a maximum propagation delay of 6ns.
Each DS1216 is shipped from Maxim with its lithium energy source disconnected, ensuring full energy
capacity. When V
CC
is first applied at a level greater than the lithium energy source is enabled for battery-
backup operation.
NONVOLATILE CONTROLLER OPERATION
FRESHNESS SEAL
5 of 15
京公网安备 11010802033920号
EEWORLD
