DAC8512: 5V, Serial Input Complete 12-Bit DAC Data
Sheet
SAMPLE AND BUY
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TECHNICAL SUPPORT
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number.
REFERENCE MATERIALS
Solutions Bulletins & Brochures
•
Digital to Analog Converters ICs Solutions Bulletin
DOCUMENT FEEDBACK
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DESIGN RESOURCES
•
DAC8512 Material Declaration
•
PCN-PDN Information
•
Quality And Reliability
•
Symbols and Footprints
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DAC8512–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
(@ V
Parameter
STATIC PERFORMANCE
Resolution
Relative Accuracy
Differential Nonlinearity
Zero-Scale Error
Full-Scale Voltage
Full-Scale Tempco
ANALOG OUTPUT
Output Current
Load Regulation at Full Scale
Capacitive Load
LOGIC INPUTS
Logic Input Low Voltage
Logic Input High Voltage
Input Leakage Current
Input Capacitance
Symbol
N
INL
DNL
V
ZSE
V
FS
TCV
FS
I
OUT
L
REG
C
L
V
IL
V
IH
I
IL
C
IL
DD
= +5.0 V
5%, –40 C
≤
T
A
≤
+85 C, unless otherwise noted)
Min
12
–1
–2
–1
4.087
4.079
Typ
Max
Units
Bits
LSB
LSB
LSB
LSB
V
V
ppm/°C
mA
LSB
pF
V
V
µA
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
nV s
nV s
2.5
1
12.5
5
0.004
mA
mA
mW
mW
%/%
Condition
Note 2
E Grade
F Grade
No Missing Codes
Data = 000
H
Data = FFF
H3
Notes 3, 4
Data = 800
H
R
L
= 402
Ω
to
∞,
Data = 800
H
No Oscillation
4
E Grade
F Grade
±
1/4
±
3/4
±
3/4
+1/2
4.095
4.095
16
±
7
1
500
+1
+2
+1
+3
4.103
4.111
±
5
3
0.8
2.4
10
10
30
30
20
15
15
30
15
10
30
20
To
±
1 LSB of Final Value
5
10
10
10
5
20
INTERFACE TIMING SPECIFICATIONS
1, 4
Clock Width High
t
CH
Clock Width Low
t
CL
Load Pulse Width
t
LDW
Data Setup
t
DS
Data Hold
t
DH
Clear Pulse Width
t
CLRW
Load Setup
t
LD1
Load Hold
t
LD2
Select
t
CSS
Deselect
t
CSH
AC CHARACTERISTICS
4
Voltage Output Settling Time
DAC Glitch
Digital Feedthrough
SUPPLY CHARACTERISTICS
Positive Supply Current
Power Dissipation
Power Supply Sensitivity
t
S
16
15
15
1.5
0.5
7.5
2.5
0.002
I
DD
P
DISS
PSS
V
IH
= 2.4 V, V
IL
= 0.8 V, No Load
V
DD
= 5 V, V
IL
= 0 V, No Load
V
IH
= 2.4 V, V
IL
= 0.8 V, No Load
V
DD
= 5 V, V
IL
= 0 V, No Load
∆V
DD
=
±
5%
NOTES
1
All input control signals are specified with tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
2
1 LSB = 1 mV for 0 V to +4.095 V output range.
3
Includes internal voltage reference error.
4
These parameters are guaranteed by design and not subject to production testing.
5
The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground. Some devices exhibit double the typical settling time in
this 6 LSB region.
Specifications subject to change without notice.
–2–
REV. A
DAC8512
WAFER TEST LIMITS
(@ V
Parameter
STATIC PERFORMANCE
Relative Accuracy
Differential Nonlinearity
Zero-Scale Error
Full-Scale Voltage
LOGIC INPUTS
Logic Input Low Voltage
Logic Input High Voltage
Input Leakage Current
SUPPLY CHARACTERISTICS
Positive Supply Current
Power Dissipation
Power Supply Sensitivity
DD
= +5.0 V
Symbol
INL
DNL
V
ZSE
V
FS
V
IL
V
IH
I
IL
I
DD
P
DISS
PSS
5%, T
A
= +25 C, applies to part number DAC8512GBC only, unless otherwise noted)
Condition
Min
–2
–1
Typ
Max
Units
LSB
LSB
LSB
V
V
V
µA
mA
mA
mW
mW
%/%
No Missing Codes
Data = 000
H
Data = FFF
H
±
3/4 +2
±
0.7 +1
+1/2 +3
4.085 4.095 4.105
0.8
2.4
10
V
IH
= 2.4 V, V
IL
= 0.8 V, No Load
V
DD
= 5 V, V
IL
= 0 V, No Load
V
IH
= 2.4 V, V
IL
= 0.8 V, No Load
V
DD
= 5 V, V
IL
= 0 V, No Load
∆V
DD
=
±
5%
1.5
0.5
7.5
2.5
0.002
2.5
1
12.5
5
0.004
NOTE
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
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