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M2GL060-1FGG484

Description
FPGA - Field Programmable Gate Array IGLOO 2
Categorysemiconductor    Programmable logic devices   
File Size2MB,25 Pages
ManufacturerMicrosemi
Websitehttps://www.microsemi.com
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M2GL060-1FGG484 Overview

FPGA - Field Programmable Gate Array IGLOO 2

M2GL060-1FGG484 Parametric

Parameter NameAttribute value
Product CategoryFPGA - Field Programmable Gate Array
ManufacturerMicrosemi
RoHSDetails
Moisture SensitiveYes
Factory Pack Quantity60
PB0121 Product Brief
IGLOO2 FPGAs Product Brief
Microsemi IGLOO
®
2 FPGAs integrate fourth generation flash-based FPGA fabric and high-performance communications interfaces
on a single chip. The IGLOO2 family is the industry’s lowest power, most reliable and highest security programmable logic solution.
This next generation IGLOO2 architecture offers up to 3.6X gate count implemented with 4-input look-up table (LUT) fabric with carry
chains, giving 2X performance, and includes multiple embedded memory options and mathblocks for digital signal processing (DSP).
High speed serial interfaces include PCI EXPRESS (PCIe), 10 Gbps attachment unit interface (XAUI) / XGMII extended sublayer
(XGXS) plus native serialization/deserialization (SERDES) communication, while double data rate 2 (DDR2)/DDR3 memory controllers
provide high speed memory interfaces.
IGLOO2 Family
High-Performance FPGA
Efficient 4-Input LUTs with Carry Chains for
High-Performance and Low Power
Up to 236 Blocks of Dual-Port 18 Kbit SRAM (Large
SRAM) with 400 MHz Synchronous Performance (512 x
36, 512 x 32, 1 Kbit x 18, 1 Kbit x 16, 2 Kbit x 9, 2 Kbit x
8, 4 Kbit x 4, 8 Kbit x 2, or 16 Kbit x 1)
Up to 240 Blocks of Three-Port 1 Kbit SRAM with 2
Read Ports and 1 Write Port (micro SRAM)
High-Performance DSP
Up to 240 Fast mathblocks with 18 x 18 Signed
Multiplication, 17 x 17 Unsigned Multiplication and
44-Bit Accumulator
High Speed Memory Interfaces
Up to 2 High Speed DDRx Memory Controllers
HPMS DDR (MDDR) and Fabric DDR (FDDR)
Controllers
Supports LPDDR/DDR2/DDR3
Maximum 333 MHz Clock Rate
SECDED Enable/Disable Feature
Supports Various DRAM Bus Width Modes, x8, x9,
x16, x18, x32, x36
Supports Command Reordering to Optimize Memory
Efficiency
Supports Data Reordering, Returning Critical Word
First for Each Command
High Speed Serial Interfaces
Up to 16 SERDES Lanes, Each Supporting:
XGXS/XAUI Extension (To Implement a 10 Gbps
(XGMII) Ethernet PHY Interface)
Native SERDES Interface Facilitates Implementation
of Serial RapidIO in Fabric or an SGMII Interface to a
soft Ethernet MAC
PCI Express (PCIe) Endpoint Controller
x1, x2, x4 Lane PCI Express Core
Up to 2 Kbytes Maximum Payload Size
64-/32-Bit AXI/AHB Master and Slave Interfaces
to the Application Layer
SDRAM Support through a Soft SDRAM Memory
Controller
64 KB Embedded SRAM (eSRAM)
Up to 512 KB Embedded Nonvolatile Memory (eNVM)
One SPI/COMM_BLK
DDR Bridge (2 Port Data R/W Buffering Bridge to DDR
Memory) with 64-Bit AXI Interface
Non-Blocking, Multi-Layer AHB Bus Matrix Allowing
Multi-Master Scheme Supporting 5 Masters and 7
Slaves
High-Performance Memory Subsystem
June 2016
© 2016 Microsemi Corporation
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