LPC5410x
32-bit ARM Cortex-M4/M0+ MCU; 104 kB SRAM; 512 kB flash,
3 x I2C, 2 x SPI, 4 x USART, 32-bit counter/ timers,
SCTimer/PWM, 12-bit 5.0 Msamples/sec ADC
Rev. 2.9 — 26 January 2018
Product data sheet
1. General description
The LPC5410x are ARM Cortex-M4 based microcontrollers for embedded applications.
These devices include an optional ARM Cortex-M0+ coprocessor, 104 kB of on-chip
SRAM, up to 512 kB on-chip flash, five general-purpose timers, one State-Configurable
Timer with PWM capabilities (SCTimer/PWM), one RTC/alarm timer, one 24-bit Multi-Rate
Timer (MRT), a Repetitive Interrupt Timer (RIT), a Windowed Watchdog Timer (WWDT),
four USARTs, two SPIs, three Fast-mode plus I
2
C-bus interfaces with high-speed slave
mode, and one 12-bit 5.0 Msamples/sec ADC.
The ARM Cortex-M4 is a 32-bit core that offers system enhancements such as low power
consumption, enhanced debug features, and a high level of support block integration. The
ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture with
separate local instruction and data buses as well as a third bus for peripherals, and
includes an internal prefetch unit that supports speculative branching. The ARM
Cortex-M4 supports single-cycle digital signal processing and SIMD instructions. A
hardware floating-point unit is integrated in the core.
The ARM Cortex-M0+ coprocessor is an energy-efficient and easy-to-use 32-bit core
which is code and tool-compatible with the Cortex-M4 core. The Cortex-M0+ coprocessor
offers up to 100 MHz performance with a simple instruction set and reduced code size. In
LPC5410x, the Cortex-M0 coprocessor hardware multiply is implemented as a 32-cycle
iterative multiplier.
2. Features and benefits
Dual processor cores: ARM Cortex-M4 and ARM Cortex-M0+. The M0+ core runs at
the same frequency as the M4 core. Both cores operate up to a maximum frequency of
100 MHz.
ARM Cortex-M4 core (version r0p1):
ARM Cortex-M4 processor, running at a frequency of up to 100 MHz, using the
same clock as the Cortex-M4.
Floating Point Unit (FPU) and Memory Protection Unit (MPU).
ARM Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC).
Non-maskable Interrupt (NMI) input with a selection of sources.
Serial Wire Debug with eight breakpoints and four watch points.
Includes Serial Wire Output for enhanced debug capabilities.
System tick timer.
NXP Semiconductors
LPC5410x
32-bit ARM Cortex-M4/M0+ microcontroller
ARM Cortex-M0+ core (version r0p1):
ARM Cortex-M0+ processor, running at a frequency of up to 100 MHz.
ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC).
Non-maskable Interrupt (NMI) input with a selection of sources.
Serial Wire Debug with four breakpoints and two watch points.
System tick timer.
On-chip memory:
Up to 512 kB on-chip flash program memory with flash accelerator and 256 byte
page erase and write.
104 kB total SRAM composed of:
Up to 96 kB contiguous main SRAM.
An additional 8 kB SRAM.
ROM API support:
Flash In-Application Programming (IAP) and In-System Programming (ISP).
Power control API.
Serial interfaces:
Four USART interfaces with synchronous mode and 32 kHz mode for wake-up
from deep sleep and power down modes. The USARTs have FIFO support from
the System FIFO and share a fractional baud-rate generator.
Two SPI interfaces, each with four slave selects and flexible data configuration.
The SPIs have FIFO support from the System FIFO. The slave function is able to
wake up the device from deep sleep and power down modes.
Three I
2
C-bus interfaces supporting fast mode and Fast-mode Plus with data rates
of up to 1Mbit/s and with multiple address recognition and monitor mode. Each
I
2
C-bus interface also supports High Speed Mode (3.4 Mbit/s) as a slave. The slave
function is able to wake up the device from deep sleep and power down modes.
Digital peripherals:
DMA controller with 22 channels and 20 programmable triggers, able to access all
memories and DMA-capable peripherals.
Up to 50 General-Purpose Input/Output (GPIO) pins. Most GPIOs have
configurable pull-up/pull-down resistors, programmable open-drain mode, and
input inverter.
GPIO registers are located on the AHB for fast access. The DMA supports GPIO
ports.
Up to eight GPIOs (pin interrupts) can be selected as edge-sensitive (rising or
falling edges or both) interrupt requests or level-sensitive (active low or active high)
interrupt requests. In addition, up to eight GPIOs can be selected to contribute a
boolean expression and interrupt generation using the pattern match engine block.
Two GPIO grouped interrupts (GINT) enable an interrupt based on a logical
(AND/OR) combination of input states.
CRC engine.
Timers:
Five 32-bit standard general purpose timers/counters, four of which support up to 4
capture inputs and 4 compare outputs, PWM mode, and external count input.
Specific timer events can be selected to generate DMA requests. The fifth timer
does not have external pin connections and may be used for internal timing
operations.
LPC5410x
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2018. All rights reserved.
Product data sheet
Rev. 2.9 — 26 January 2018
2 of 90
NXP Semiconductors
LPC5410x
32-bit ARM Cortex-M4/M0+ microcontroller
One State Configurable Timer/PWM (SCT/PWM) with 8 inputs (6 external inputs
and 2 internal inputs) and 8 output functions (including capture and match). Inputs
and outputs can be routed to/from external pins and internally to/from selected
peripherals. Internally, the SCT supports 13 captures/matches, 13 events and 13
states.
32-bit Real-time clock (RTC) with 1 s resolution running in the always-on power
domain. A timer in the RTC can be used for wake-up from all low power modes
including deep power-down, with 1 ms resolution.
Multiple-channel multi-rate 24-bit timer (MRT) for repetitive interrupt generation at
up to four programmable, fixed rates.
Windowed Watchdog Timer (WWDT).
Ultra-low power Micro-tick Timer, running from the Watchdog oscillator, that can be
used to wake up the device from low power modes.
Repetitive Interrupt Timer (RIT) for debug time-stamping and general-purpose use.
Analog peripheral: 12-bit, 12-channel, Analog-to-Digital Converter (ADC) supporting
5.0 Msamples/s. The ADC supports two independent conversion sequences.
Clock generation:
12 MHz internal RC oscillator.
External clock input for clock frequencies of up to 25 MHz.
Internal low-power, watchdog oscillator (WDOSC) with a nominal frequency of 500
kHz.
32 kHz low-power RTC oscillator.
System PLL allows CPU operation up to the maximum CPU rate. May be run from
the internal RC oscillator, the external clock input CLKIN, or the RTC oscillator.
Clock output function for monitoring internal clocks.
Frequency measurement unit for measuring the frequency of any on-chip or
off-chip clock signal.
Power-saving modes and wake-up:
Integrated PMU (Power Management Unit) to minimize power consumption.
Reduced power modes: sleep, deep sleep, power down, and deep power-down.
Wake-up from deep sleep and power down modes via activity on the USART, SPI,
and I
2
C peripherals.
Wake-up from sleep, deep sleep, power down, and deep power-down modes using
the RTC alarm.
Single power supply 1.62 V to 3.6 V.
Power-On Reset (POR).
Brown-Out Detect (BOD) with separate thresholds for interrupt and forced reset.
JTAG boundary scan supported.
Unique device serial number (128 bit) for identification.
Operating temperature range
40
°C to 105 °C.
Available in a 3.288 x 3.288 mm WLCSP49 package and LQFP64 package.
LPC5410x
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2018. All rights reserved.
Product data sheet
Rev. 2.9 — 26 January 2018
3 of 90
NXP Semiconductors
LPC5410x
32-bit ARM Cortex-M4/M0+ microcontroller
3. Ordering information
Table 1.
Ordering information
Package
Name
Description
Version
Type number
LPC54102J512UK49 WLCSP49 wafer level chip-size package; 49 (7 x 7) bumps; 3.288 x 3.288 x 0.54 mm -
LPC54102J256UK49 WLCSP49 wafer level chip-size package; 49 (7 x 7) bumps; 3.288 x 3.288 x 0.54 mm -
LPC54101J512UK49 WLCSP49 wafer level chip-size package; 49 (7 x 7) bumps; 3.288 x 3.288 x 0.54 mm -
LPC54101J256UK49 WLCSP49 wafer level chip-size package; 49 (7 x 7) bumps; 3.288 x 3.288 x 0.54 mm -
LPC54102J512BD64 LQFP64
LPC54102J256BD64 LQFP64
LPC54101J512BD64 LQFP64
LPC54101J256BD64 LQFP64
plastic low profile quad flat package; 64 leads; body 10
10
1.4 mm
plastic low profile quad flat package; 64 leads; body 10
10
1.4 mm
plastic low profile quad flat package; 64 leads; body 10
10
1.4 mm
plastic low profile quad flat package; 64 leads; body 10
10
1.4 mm
SOT314-2
SOT314-2
SOT314-2
SOT314-2
3.1 Ordering options
Table 2.
Ordering options
Device order part number Flash/kB
LPC54102J512UK49Z
LPC54102J256UK49Z
LPC54101J512UK49Z
LPC54101J256UK49Z
LPC54102J512BD64QL
LPC54102J256BD64QL
LPC54101J512BD64QL
LPC54101J256BD64QL
[1]
Type number
LPC54102J512UK49
LPC54102J256UK49
LPC54101J512UK49
LPC54101J256UK49
LPC54102J512BD64
LPC54102J256BD64
LPC54101J512BD64
LPC54101J256BD64
Total SRAM/kB
104
104
104
104
104
104
104
104
Core M4 w/ FPU
1
1
1
1
1
1
1
1
Core
M0+
1
1
0
0
1
1
0
0
GPIO
39
39
39
39
50
50
50
50
512
256
512
256
512
256
512
256
All of the parts include five 32-bit general-purpose timers, one State-Configurable Timer with PWM
capabilities (SCTimer/PWM), one RTC/alarm timer, one 24-bit Multi-Rate Timer (MRT), a Windowed
Watchdog Timer (WWDT), four USARTs, two SPIs, three Fast-mode plus I2C-bus interfaces with
high-speed slave mode, and one 12-bit 5.0 Msamples/sec ADC.
4. Marking
Terminal 1
index area
n
Terminal 1 index area
1
aaa-011231
aaa-015675
Fig 1.
LPC5410x
LQFP64 package marking
Fig 2.
WLCSP49 package marking
© NXP B.V. 2018. All rights reserved.
All information provided in this document is subject to legal disclaimers.
Product data sheet
Rev. 2.9 — 26 January 2018
4 of 90
NXP Semiconductors
LPC5410x
32-bit ARM Cortex-M4/M0+ microcontroller
The LPC5410x LQFP64 package has the following top-side marking:
•
First line: LPC5410xJyyy
–
x: 2 = dual core (M4, M0+), 1 = single core (M4)
–
yyy: flash size
•
Second line: BD64
•
Third line: xxxxxxxxxxxx
•
Fourth line: xxxyywwx[R]z
–
yyww: Date code with yy = year and ww = week.
–
xR = boot code version and device revision.
The LPC5410x WLCSP49 package has the following top-side marking:
•
First line: LPC5410x
–
x: 2 = dual core (M4, M0+), 1 = single core (M4)
•
Second line: JxxxUK49
–
xxx: flash size
•
Third line: xxxxxxxx
•
Fourth line: xxxyyww
–
yyww: Date code with yy = year and ww = week.
•
Fifth line: xxxxx
•
Sixth line: NXP x[R]z
–
xR = boot code version and device revision.
Table 3.
‘1B’
‘1C’
Device revision table
Revision description
Initial device revision with boot code version 17.1.
Second device revision with boot code version 17.1.
Revision identifier (R)
LPC5410x
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2018. All rights reserved.
Product data sheet
Rev. 2.9 — 26 January 2018
5 of 90
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