1.6 GHz Clock Distribution IC,
Dividers, Delay Adjust, Three Outputs
AD9514
FEATURES
1.6 GHz differential clock input
3 programmable dividers
Divide-by in range from1 to 32
Phase select for coarse delay adjust
2 independent 1.6 GHz LVPECL clock outputs
Additive broadband output jitter 225 fs rms
1 independent 800 MHz/250 MHz LVDS/CMOS clock output
Additive broadband output jitter 300 fs rms/290 fs rms
Time delays up to 10 ns
Device configured with 4-level logic pins
Space-saving, 32-lead LFCSP
FUNCTIONAL BLOCK DIAGRAM
RSET
VS
GND
AD9514
/1. . . /32
LVPECL
OUT0
OUT0B
LVPECL
CLK
CLKB
/1. . . /32
OUT1
OUT1B
LVDS/CMOS
OUT2
/1. . . /32
t
SYNCB
OUT2B
APPLICATIONS
Low jitter, low phase noise clock distribution
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
High performance instrumentation
Broadband infrastructure
ATE
SETUP LOGIC
05596-001
VREF
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Figure 1.
GENERAL DESCRIPTION
The AD9514 features a multi-output clock distribution IC in a
design that emphasizes low jitter and phase noise to maximize
data converter performance. Other applications with
demanding phase noise and jitter requirements also benefit from
this part.
There are three independent clock outputs. Two of the outputs
are LVPECL, and the third output can be set to either LVDS or
CMOS levels. The LVPECL outputs operate to 1.6 GHz, and
the third output operates to 800 MHz in LVDS mode and to
250 MHz in CMOS mode.
Each output has a programmable divider that can be set to
divide by a selected set of integers ranging from 1 to 32. The
phase of one clock output relative to another clock output can
be set by means of a divider phase select function that serves as
a coarse timing adjustment.
The LVDS/CMOS output features a delay element with three
selectable full-scale delay values (1.5 ns, 5 ns, and 10 ns), each
with 16 steps of fine adjustment.
The AD9514 does not require an external controller for
operation or setup. The device is programmed by means of
11 pins (S0 to S10) using 4-level logic. The programming pins
are internally biased to ⅓ V
S
. The VREF pin provides a level of
⅔ V
S
. V
S
(3.3 V) and GND (0 V) provide the other two logic levels.
The AD9514 is ideally suited for data converter clocking
applications where maximum converter performance is
achieved by encode signals with subpicosecond jitter.
The AD9514 is available in a 32-lead LFCSP and operates from
a single 3.3 V supply. The temperature range is −40°C to
+85°C.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice.
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Fax: 781.461.3113 © 2005–2020 Analog Devices, Inc. All rights reserved.
AD9514
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ...................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications .................................................................................... 3
Clock Input ................................................................................... 3
Clock Outputs ............................................................................... 3
Timing Characteristics ................................................................ 4
Clock Output Phase Noise .......................................................... 5
Clock Output Additive Time Jitter ............................................ 8
SYNCB, VREF, and Setup Pins ................................................ 10
Power ........................................................................................... 10
Timing Diagrams............................................................................ 11
Absolute Maximum Ratings ......................................................... 12
Thermal Characteristics ............................................................ 12
ESD Caution................................................................................ 12
Pin Configuration and Function Descriptions .......................... 13
Terminology .................................................................................... 14
Typical Performance Characteristics ........................................... 15
Functional Description .................................................................. 18
Overall .......................................................................................... 18
CLK, CLKB—Differential Clock Input ................................... 18
Synchronization.......................................................................... 18
Power-On SYNC .................................................................... 18
SYNCB ..................................................................................... 18
R
SET
Resistor ................................................................................ 19
VREF ............................................................................................ 19
Setup Configuration .................................................................. 19
Divider Phase Offset .................................................................. 22
Delay Block ................................................................................. 22
Outputs ........................................................................................ 23
Power Supply .............................................................................. 23
Exposed Metal Paddle ........................................................... 24
Power Management ................................................................... 24
Applications .................................................................................... 25
Using the AD9514 Outputs for ADC Clock Applications ... 25
LVPECL Clock Distribution..................................................... 25
LVDS Clock Distribution.......................................................... 26
CMOS Clock Distribution ........................................................ 26
Setup Pins (S0 to S10) ................................................................ 26
Power and Grounding Considerations and Power Supply
Rejection ...................................................................................... 26
Phase Noise and Jitter Measurement Setups .......................... 27
Outline Dimensions ....................................................................... 28
Ordering Guide .......................................................................... 28
REVISION HISTORY
11/2020—Rev. 0 to Rev. A
Changed CP-32-2 to CP-32-7 ...................................... Throughout
Changes to Figure 6........................................................................ 13
Updated Outline Dimensions ....................................................... 28
Changes to Ordering Guide .......................................................... 28
7/2005—Revision 0: Initial Version
Rev. A | Page 2 of 28
AD9514
SPECIFICATIONS
Typical (typ) is given for V
S
= 3.3 V ± 5%, T
A
= 25°C, R
SET
= 4.12 kΩ, LVPECL V
OD
= 790 mV, unless otherwise noted. Minimum (min)
and maximum (max) values are given over full V
S
and T
A
(−40°C to +85°C) variation.
CLOCK INPUT
Table 1.
Parameter
CLOCK INPUT (CLK)
Input Frequency
1
Input Sensitivity
1
Input Common-Mode Voltage, V
CM
Input Common-Mode Range, V
CMR
Input Sensitivity, Single-Ended
Input Resistance
Input Capacitance
1
Min
0
1.5
1.3
4.0
Typ
Max
1.6
Unit
GHz
mV p-p
V
V
mV p-p
kΩ
pF
Test Conditions/Comments
150
1.6
150
4.8
2
1.7
1.8
5.6
Self-biased; enables ac coupling
With 200 mV p-p signal applied; dc-coupled
CLK ac-coupled; CLKB ac-bypassed to RF ground
Self-biased
A slew rate of 1 V/ns is required to meet jitter, phase noise, and propagation delay specifications.
CLOCK OUTPUTS
Table 2.
Parameter
LVPECL CLOCK OUTPUTS
(OUT0, OUT1) Differential
Output Frequency
Output High Voltage (V
OH
)
Output Low Voltage (V
OL
)
Output Differential Voltage (V
OD
)
LVDS CLOCK OUTPUT
(OUT2) Differential
Output Frequency
Differential Output Voltage (V
OD
)
Delta V
OD
Output Offset Voltage (V
OS
)
Delta V
OS
Short-Circuit Current (I
SA
, I
SB
)
CMOS CLOCK OUTPUT
(OUT2) Single-Ended
Output Frequency
Output Voltage High (V
OH
)
Output Voltage Low (V
OL
)
Min
Typ
Max
Unit
Test Conditions/Comments
Termination = 50 Ω to V
S
− 2 V
0
V
S
− 1.1
V
S
− 1.90
640
V
S
− 0.96
V
S
− 1.76
790
1.6
V
S
− 0.82
V
S
− 1.52
960
GHz
V
V
mV
Termination = 100 Ω differential
0
250
1.125
350
1.23
14
800
450
30
1.375
25
24
MHz
mV
mV
V
mV
mA
0
V
S
− 0.1
250
0.1
MHz
V
V
Output shorted to GND
Single-ended measurements; termination open
Complementary output on (OUT2B)
With 5 pF load
@ 1 mA load
@ 1 mA load
Rev. A | Page 3 of 28
AD9514
TIMING CHARACTERISTICS
CLK input slew rate = 1 V/ns or greater.
Table 3.
Parameter
LVPECL
Output Rise Time, t
RP
Output Fall Time, t
FP
PROPAGATION DELAY, t
PECL
, CLK-TO-LVPECL OUT
Divide = 1
Divide = 2 − 32
Variation with Temperature
OUTPUT SKEW, LVPECL
OUT0 to OUT1 on Same Part, t
SKP1
Both LVPECL Outputs Across Multiple Parts, t
SKP_AB2
Same LVPECL Output Across Multiple Parts, t
SKP_AB2
LVDS
Output Rise Time, t
RL
Output Fall Time, t
FL
PROPAGATION DELAY, t
LVDS
, CLK-TO-LVDS OUT
Divide = 1
Divide = 2 − 32
Variation with Temperature
OUTPUT SKEW, LVDS
LVDS Output Across Multiple Parts, t
SKV_AB2
CMOS
Output Rise Time, t
RC
Output Fall Time, t
FC
PROPAGATION DELAY, t
CMOS
, CLK-TO-CMOS OUT
Divide = 1
Divide = 2 − 32
Variation with Temperature
OUTPUT SKEW, CMOS
CMOS Output Across Multiple Parts, t
SKC_AB2
LVPECL-TO-LVDS OUT
Output Delay, t
SKV_C
LVPECL-TO-CMOS OUT
Output Delay, t
SKV_C
DELAY ADJUST (OUT2; LVDS and CMOS)
S0 = 1/3
Zero Scale Delay Time
3
Zero Scale Variation with Temperature
Full Scale Time Delay
3
Full Scale Variation with Temperature
S0 = 2/3
Zero Scale Delay Time
3
Zero Scale Variation with Temperature
Full Scale Time Delay
3
Full Scale Variation with Temperature
Min
Typ
60
60
355
395
480
530
0.5
0
Max
100
100
635
710
Unit
ps
ps
ps
ps
ps/°C
ps
ps
ps
ps
ps
ns
ns
ps/°C
Optional delay off
230
650
650
1.10
1.15
1.45
1.50
1
865
990
1.75
1.80
ps
ps
ps
ns
ns
ps/°C
Optional delay off
300
560
700
790
970
950
1150
ps
ps
ps
B outputs are inverted; termination = open
20% to 80%; C
LOAD
= 3 pF single-ended
80% to 20%; C
LOAD
= 3 pF single-ended
Optional delay off
Termination = 100 Ω differential, 3.5 mA
20% to 80%, measured differentially
80% to 20%, measured differentially
Optional delay off
Test Conditions/Comments
Termination = 50 Ω to V
S
− 2 V
20% to 80%, measured differentially
80% to 20%, measured differentially
−50
+55
125
125
350
350
1.55
1.60
200
210
1.00
1.05
1.25
1.30
0.9
0.34
0.20
1.7
−0.38
0.45
0.31
5.9
−1.3
ns
ps/°C
ns
ps/°C
ns
ps/°C
ns
ps/°C
Rev. A | Page 4 of 28
AD9514
Parameter
S0 = 1
Zero Scale Delay Time
3
Zero Scale Variation with Temperature
Full Scale Time Delay
3
Full Scale Variation with Temperature
Linearity, DNL
Linearity, INL
1
2
Min
Typ
0.56
0.47
11.4
−5
0.2
0.2
Max
Unit
ns
ps/°C
ns
ps/°C
LSB
LSB
Test Conditions/Comments
This is the difference between any two similar delay paths within a single device operating at the same voltage and temperature.
This is the difference between any two similar delay paths across multiple devices operating at the same voltage and temperature.
3
Incremental delay; does not include propagation delay.
CLOCK OUTPUT PHASE NOISE
CLK input slew rate = 1 V/ns or greater.
Table 4.
Parameter
CLK-TO-LVPECL ADDITIVE PHASE NOISE
CLK = 622.08 MHz, OUT = 622.08 MHz
Divide = 1
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
>1 MHz Offset
CLK = 622.08 MHz, OUT = 155.52 MHz
Divide = 4
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
>1 MHz Offset
CLK = 622.08 MHz, OUT = 38.88 MHz
Divide = 16
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
>1 MHz Offset
CLK = 491.52 MHz, OUT = 61.44 MHz
Divide = 8
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
>1 MHz Offset
Min
Typ
Max
Unit
Test Conditions/Comments
−125
−132
−140
−148
−153
−154
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−128
−140
−148
−155
−161
−161
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−135
−145
−158
−165
−165
−166
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−131
−142
−153
−160
−165
−165
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Rev. A | Page 5 of 28
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