DS33Z44
Quad Ethernet Mapper
www.maxim-ic.com
GENERAL DESCRIPTION
The DS33Z44 extends four 10/100 Ethernet LAN
segments by encapsulating MAC frames in HDLC or
X.86 (LAPS) for transmission over four PDH/TDM
data streams. The serial links support bidirectional
synchronous interconnect up to 52Mbps over xDSL,
T1/E1/J1, T3/E3, V.35/Optical, OC-1/EC-1, or
SONET/SDH Tributary.
The device performs store-and-forward of packets
with full wire-speed transport capability. The built-in
Committed Information Rate (CIR) controllers
provide fractional bandwidth allocation up to the line
rate in increments of 512kbps. The DS33Z44 can
operate with an inexpensive external processor,
EEPROM or in a stand-alone hardware mode.
FEATURES
Four 10/100 IEEE 802.3 Ethernet MACs (MII
and RMII) Half/Full-Duplex with Automatic Flow
Control
Four 52Mbps Synchronous TDM Serial Ports
with Independent Transmit and Receive Timing
HDLC/LAPS Encapsulation with Programmable
FCS and Interframe Fill
Committed Information Rate Controllers Provide
Fractional Allocations in 512kbps Increments
Programmable BERT for Serial (TDM)
Interfaces
External 16MB, 100MHz SDRAM Buffering
APPLICATIONS
Transparent LAN Service
LAN Extension
Ethernet Delivery Over T1/E1/J1, T3/E3,
OC-1/EC-1, G.SHDSL, or HDSL2/4
Parallel Microprocessor Interface
SPI Interface and Hardware Mode for Operation
Without a Host Processor
1.8V Operation with 3.3V Tolerant I/O
IEEE 1149.1 JTAG Support
Features Continued on Page
9.
FUNCTIONAL DIAGRAM
DS33Z44
4 SERIAL
PORTS
TRANSCEIVERS/
SERIAL DRIVERS
ORDERING INFORMATION
PART
TEMP RANGE
-40°C to +85°C
PIN-PACKAGE
256 CSBGA
DS33Z44
BERT
CONFIG.
LOADER
HDLC/X.86
MAPPER
PROM
OR
μC
SDRAM
Go to
www.maxim-ic.com/telecom
for a complete list of
Telecommunications data sheets, evaluation kits, application notes,
and software downloads.
4 10/100
MACs
4 MII/RMII
4 10/100
ETHERNET
PHYs
Note:
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:
www.maxim-ic.com/errata.
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REV: 122006
DS33Z44 Quad Ethernet Mapper
TABLE OF CONTENTS
1
2
DESCRIPTION ....................................................................................................................8
FEATURE HIGHLIGHTS ....................................................................................................9
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
G
ENERAL
......................................................................................................................................9
S
ERIAL
I
NTERFACES
......................................................................................................................9
HDLC...........................................................................................................................................9
C
OMMITTED
I
NFORMATION
R
ATE
(CIR) C
ONTROLLERS
...................................................................9
X.86 S
UPPORT
..............................................................................................................................9
SDRAM I
NTERFACE
....................................................................................................................10
MAC I
NTERFACES
.......................................................................................................................10
M
ICROPROCESSOR
I
NTERFACE
....................................................................................................10
S
ERIAL
SPI I
NTERFACE
—M
ASTER
M
ODE
O
NLY
............................................................................10
D
EFAULT
C
ONFIGURATIONS
.........................................................................................................10
T
EST AND
D
IAGNOSTICS
..............................................................................................................10
S
PECIFICATIONS
C
OMPLIANCE
.....................................................................................................11
3
4
5
6
7
8
APPLICATIONS................................................................................................................12
ACRONYMS AND GLOSSARY........................................................................................15
MAJOR OPERATING MODES .........................................................................................16
BLOCK DIAGRAMS .........................................................................................................17
PIN DESCRIPTIONS.........................................................................................................18
7.1
8.1
P
IN
F
UNCTIONAL
D
ESCRIPTION
....................................................................................................18
P
ROCESSOR
I
NTERFACE
..............................................................................................................29
Read-Write/Data Strobe Modes..........................................................................................................30
Clear On Read ....................................................................................................................................30
Interrupt and Pin Modes .....................................................................................................................30
FUNCTIONAL DESCRIPTION..........................................................................................29
8.1.1
8.1.2
8.1.3
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
8.11
8.12
SPI S
ERIAL
EEPROM I
NTERFACE
...............................................................................................30
C
LOCK
S
TRUCTURE
.....................................................................................................................31
Serial Interface Clock Modes..............................................................................................................33
Ethernet Interface Clock Modes .........................................................................................................33
8.3.1
8.3.2
R
ESETS AND
L
OW
-P
OWER
M
ODES
...............................................................................................34
INITIALIZATION AND CONFIGURATION .................................................................................35
G
LOBAL
R
ESOURCES
..................................................................................................................35
P
ER
-P
ORT
R
ESOURCES
..............................................................................................................35
D
EVICE
I
NTERRUPTS
...................................................................................................................36
S
ERIAL
I
NTERFACES
....................................................................................................................38
C
ONNECTIONS AND
Q
UEUES
........................................................................................................38
A
RBITER
.....................................................................................................................................40
F
LOW
C
ONTROL
..........................................................................................................................41
8.12.1 Full-Duplex Flow Control ....................................................................................................................42
8.12.2 Half-Duplex Flow Control....................................................................................................................43
8.12.3 Host-Managed Flow Control ...............................................................................................................43
8.13 E
THERNET
I
NTERFACES
...............................................................................................................44
8.13.1 DTE and DCE Mode ...........................................................................................................................46
8.14 E
THERNET
MAC..........................................................................................................................47
8.14.1 MII Mode Options................................................................................................................................49
8.14.2 RMII Mode ..........................................................................................................................................50
8.14.3 PHY MII Management Block and MDIO Interface ..............................................................................51
8.15 BERT .........................................................................................................................................52
8.15.1 BERT Features ...................................................................................................................................52
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DS33Z44 Quad Ethernet Mapper
8.15.2
8.15.3
8.15.4
8.15.5
Receive Data Interface .......................................................................................................................52
Repetitive Pattern Synchronization ....................................................................................................53
Pattern Monitoring...............................................................................................................................54
Pattern Generation..............................................................................................................................54
8.16
8.17
8.18
8.19
8.20
8.21
S
ERIAL
I
NTERFACES
....................................................................................................................55
T
RANSMIT
P
ACKET
P
ROCESSOR
..................................................................................................55
R
ECEIVE
P
ACKET
P
ROCESSOR
....................................................................................................56
X.86 E
NCODING AND
D
ECODING
..................................................................................................58
C
OMMITTED
I
NFORMATION
R
ATE
C
ONTROLLER
............................................................................61
H
ARDWARE
M
ODE
.......................................................................................................................63
R
EGISTER
B
IT
M
APS
....................................................................................................................68
Global Register Bit Map ......................................................................................................................68
Arbiter Register Bit Map......................................................................................................................69
BERT Register Bit Map.......................................................................................................................69
Serial Interface Register Bit Map ........................................................................................................70
Ethernet Interface Register Bit Map....................................................................................................72
MAC Register Bit Map ........................................................................................................................73
9
DEVICE REGISTERS .......................................................................................................67
9.1
9.1.1
9.1.2
9.1.3
9.1.4
9.1.5
9.1.6
9.2
9.3
9.4
9.5
G
LOBAL
R
EGISTER
D
EFINITIONS
..................................................................................................75
A
RBITER
R
EGISTERS
...................................................................................................................91
Arbiter Register Bit Descriptions.........................................................................................................91
9.3.1
BERT R
EGISTERS
.......................................................................................................................94
S
ERIAL
I
NTERFACE
R
EGISTERS
..................................................................................................101
Serial Interface Transmit and Common Registers............................................................................101
Serial Interface Transmit Register Bit Descriptions ..........................................................................101
Transmit HDLC Processor Registers ...............................................................................................102
X.86 Registers ..................................................................................................................................108
Receive Serial Interface....................................................................................................................110
Ethernet Interface Register Bit Descriptions.....................................................................................123
MAC Registers..................................................................................................................................135
9.5.1
9.5.2
9.5.3
9.5.4
9.5.5
9.6
E
THERNET
I
NTERFACE
R
EGISTERS
............................................................................................123
9.6.1
9.6.2
10 FUNCTIONAL TIMING....................................................................................................152
10.1 F
UNCTIONAL
S
ERIAL
I/O T
IMING
.................................................................................................152
10.2 MII
AND
RMII I
NTERFACES
.........................................................................................................153
10.3 SPI I
NTERFACE
M
ODE AND
EEPROM P
ROGRAM
S
EQUENCE
.....................................................155
11 OPERATING PARAMETERS .........................................................................................158
11.1 T
HERMAL
C
HARACTERISTICS
.....................................................................................................160
11.2 MII I
NTERFACE
..........................................................................................................................161
11.3 RMII I
NTERFACE
.......................................................................................................................163
11.4 MDIO I
NTERFACE
......................................................................................................................165
11.5 T
RANSMIT
WAN I
NTERFACE
......................................................................................................166
11.6 R
ECEIVE
WAN I
NTERFACE
........................................................................................................167
11.7 SDRAM T
IMING
........................................................................................................................168
11.8 M
ICROPROCESSOR
B
US
AC C
HARACTERISTICS
.........................................................................170
11.9 EEPROM I
NTERFACE
T
IMING
....................................................................................................173
11.10 JTAG I
NTERFACE
T
IMING
..........................................................................................................174
12 JTAG INFORMATION.....................................................................................................175
12.1 JTAG/TAP C
ONTROLLER
S
TATE
M
ACHINE
D
ESCRIPTION
...........................................................176
12.2 TAP C
ONTROLLER
S
TATE
M
ACHINE
...........................................................................................176
12.2.1
12.2.2
12.2.3
12.2.4
Test-Logic-Reset...............................................................................................................................176
Run-Test-Idle ....................................................................................................................................176
Select-DR-Scan ................................................................................................................................176
Capture-DR.......................................................................................................................................176
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DS33Z44 Quad Ethernet Mapper
12.2.5 Shift-DR ............................................................................................................................................176
12.2.6 Exit1-DR............................................................................................................................................176
12.2.7 Pause-DR .........................................................................................................................................176
12.2.8 Exit2-DR............................................................................................................................................176
12.2.9 Update-DR ........................................................................................................................................177
12.2.10 Select-IR-Scan..................................................................................................................................177
12.2.11 Capture-IR ........................................................................................................................................177
12.2.12 Shift-IR ..............................................................................................................................................177
12.2.13 Exit1-IR .............................................................................................................................................177
12.2.14 Pause-IR ...........................................................................................................................................177
12.2.15 Exit2-IR .............................................................................................................................................177
12.2.16 Update-IR..........................................................................................................................................177
12.3 I
NSTRUCTION
R
EGISTER
............................................................................................................178
12.3.1
12.3.2
12.3.3
12.3.4
12.3.5
12.3.6
SAMPLE:PRELOAD .........................................................................................................................179
BYPASS............................................................................................................................................179
EXTEST ............................................................................................................................................179
CLAMP..............................................................................................................................................179
HIGHZ ...............................................................................................................................................179
IDCODE ............................................................................................................................................179
12.4 JTAG ID C
ODES
.......................................................................................................................180
12.5 T
EST
R
EGISTERS
......................................................................................................................180
12.5.1 Boundary Scan Register...................................................................................................................180
12.5.2 Bypass Register................................................................................................................................180
12.5.3 Identification Register .......................................................................................................................180
12.6 JTAG F
UNCTIONAL
T
IMING
........................................................................................................181
13 PACKAGE INFORMATION ............................................................................................182
13.1 256-CSBGA (17
MM X
17
MM
) (56-G6017-001) ..........................................................................182
14 REVISION HISTORY ......................................................................................................183
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DS33Z44 Quad Ethernet Mapper
LIST OF FIGURES
Figure 3-1. Ethernet-to-WAN Extension (No Framing) ........................................................................................... 12
Figure 3-2. Ethernet-to-WAN Extension (T1/E1 Framing and LIU)......................................................................... 13
Figure 3-3. Ethernet-to-WAN Extension with T3/E3 Framing ................................................................................. 13
Figure 3-4. Ethernet Over DSL................................................................................................................................ 14
Figure 3-5. Copper-to-Fiber Connection ................................................................................................................. 14
Figure 6-1. Detailed Block Diagram ........................................................................................................................ 17
Figure 7-1. 256-Ball CSBGA Pinout ........................................................................................................................ 28
Figure 8-1. Clocking for the DS33Z44..................................................................................................................... 32
Figure 8-2. Device Interrupt Information Flow Diagram .......................................................................................... 37
Figure 8-3. Transmit Connection Diagram .............................................................................................................. 39
Figure 8-4. Receive Connection Diagram ............................................................................................................... 40
Figure 8-5. Flow Control Using Pause Control Frame ............................................................................................ 43
Figure 8-6. IEEE 802.3 Ethernet Frame.................................................................................................................. 44
Figure 8-7. Configured as DTE Connected to an Ethernet PHY in MII Mode......................................................... 46
Figure 8-8. DS33Z44 Configured as a DCE in MII Mode........................................................................................ 47
Figure 8-9. RMII Interface........................................................................................................................................ 50
Figure 8-10. MII Management Frame...................................................................................................................... 51
Figure 8-11. PRBS Synchronization State Diagram ............................................................................................... 53
Figure 8-12. Repetitive Pattern Synchronization State Diagram ............................................................................ 54
Figure 8-13. LAPS Encoding of MAC Frames Concept .......................................................................................... 58
Figure 8-14. X.86 Encapsulation of the MAC Field ................................................................................................. 59
Figure 8-15. CIR in the WAN Transmit Path ........................................................................................................... 62
Figure 10-1. Tx Serial Interface Functional Timing ............................................................................................... 152
Figure 10-2. Rx Serial Interface Functional Timing............................................................................................... 152
Figure 10-3. Transmit Byte Sync Functional timing .............................................................................................. 153
Figure 10-4. Receive Byte Sync Functional Timing .............................................................................................. 153
Figure 10-5. MII Transmit Functional Timing......................................................................................................... 154
Figure 10-6. MII Transmit Half-Duplex with a Collision Functional Timing ........................................................... 154
Figure 10-7. MII Receive Functional Timing.......................................................................................................... 154
Figure 10-8. RMII Transmit Interface Functional Timing....................................................................................... 154
Figure 10-9. RMII Receive Interface Functional Timing........................................................................................ 155
Figure 10-10. SPI Master Functional Timing......................................................................................................... 155
Figure 11-1. Transmit MII Interface Timing ........................................................................................................... 161
Figure 11-2. Receive MII Interface Timing ............................................................................................................ 162
Figure 11-3. Transmit RMII Interface .................................................................................................................... 163
Figure 11-4. Receive RMII Interface Timing.......................................................................................................... 164
Figure 11-5. MDIO Interface Timing...................................................................................................................... 165
Figure 11-6. Transmit WAN Interface Timing........................................................................................................ 166
Figure 11-7. Receive WAN Interface Timing......................................................................................................... 167
Figure 11-8. SDRAM Interface Timing .................................................................................................................. 169
Figure 11-9. Intel Bus Read Timing (HWMODE = 0, MODEC = 00) .................................................................... 171
Figure 11-10. Intel Bus Write Timing (HWMODE = 0, MODEC = 00)................................................................... 171
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