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932S421BGLFT

Description
Buffers u0026 Line Drivers Octal Buf/Line Drv
Categorysemiconductor    Analog mixed-signal IC   
File Size218KB,23 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
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932S421BGLFT Overview

Buffers u0026 Line Drivers Octal Buf/Line Drv

932S421BGLFT Parametric

Parameter NameAttribute value
Product CategoryClock Synthesizer / Jitter Cleaner
ManufacturerIDT (Integrated Device Technology, Inc.)
RoHSDetails
Number of Outputs19 Output
Output LevelHCSL
Max Output Freq48 MHz
Input LevelCrystal
Maximum Input Frequency14.31818 MHz
Supply Voltage - Max3.465 V
Supply Voltage - Min3.135 V
Maximum Operating Temperature+ 70 C
Minimum Operating Temperature0 C
Mounting StyleSMD/SMT
Package / CaseTSSOP-56
PackagingReel
PackagingCut Tape
PackagingMouseReel
Height1 mm
Length14 mm
Operating Supply Current350 mA
Factory Pack Quantity2000
Width6.1 mm
Unit Weight0.026103 oz
DATASHEET
PCIe Gen2 and QPI Clock for Intel-Based Servers
Recommended Application:
PCIe Gen 2 & QPI compliant CK410B+ clock for Intel-based
servers
Output Features:
4 - 0.7V current-mode differential CPU pairs
5 - 0.7V current-mode differential SRC pair
4 - PCI (33MHz)
3 - PCICLK_F, (33MHz) free-running
1 - 48MHz
2 - REF, 14.318MHz
Features/Benefits:
Supports spread spectrum modulation, 0 to -0.5%
down spread
Uses external 14.318MHz crystal and external load
capacitors for low ppm synthesis error
CPU clocks independent of SRC/PCI clocks
D2/D3 SMBus address
ICS932S421B
Key Specifications:
PCIe Gen 2 compliant SRC outputs
QPI & FBD 2 compliant CPU clocks
CPU cycle-cycle jitter: < 50ps
SRC cycle-cycle jitter: < 125ps
PCI cycle-cycle jitter: < 500ps
CPU output skew: < 50ps
SRC output skew: < 250ps
± 100ppm frequency accuracy on all outputs
Functionality
FS_C
0
0
0
0
1
1
1
1
1
FS_B
0
0
1
1
0
0
1
1
1
FS_A
0
1
0
1
0
1
0
1
2
CPU
MHz
266.67
133.33
200.00
166.67
333.33
100.00
400.00
SRC
MHz
PCI
MHz
REF
MHz
U
SB
MHz
100.00
33.33
14.32
48.00
Reserved
1. FS_B and FS_C are three-level inputs. Please see V
IL_FS
and V
IH_FS
specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FS_A is a low-threshold input. Please see the V
IL_FS
and V
IH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
Pin Configuration
VDDPCI
GNDPCI
PCICLK0
PCICLK1
PCICLK2
PCICLK3
GNDPCI
VDDPCI
PCICLK_F0
PCICLK_F1
PCICLK_F2
VDD48
48MHz
GND48
VDDSRC
SRCCLKT0
SRCCLKC0
SRCCLKC1
SRCCLKT1
GNDSRC
SRCCLKT2
SRCCLKC2
SRCCLKC3
SRCCLKT3
VDDSRC
SRCCLKT4
SRCCLKC4
VDDSRC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
FS_C/TEST_SEL
REF0
REF1
VDDREF
X1
X2
GNDREF
FS_B/TEST_MODE
FS_A
VDDCPU
CPUCLKT0
CPUCLKC0
VDDCPU
CPUCLKT1
CPUCLKC1
GNDCPU
CPUCLKT2
CPUCLKC2
VDDCPU
CPUCLKT3
CPUCLKC3
VDDA
GNDA
IREF
NC
Vtt_PwrGd#/PD
SDATA
SCLK
56-pin SSOP & TSSOP
IDT
TM
PCIe Gen2 and QPI Clock for Intel-Based Servers
ICS932S421
1340G—01/26/10
1
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