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74LVC544AD

Description
Bus Transceivers OCTAL LATCHED TRANSCEIVER W/DU
Categorylogic    logic   
File Size135KB,19 Pages
ManufacturerNXP
Websitehttps://www.nxp.com
Environmental Compliance
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74LVC544AD Overview

Bus Transceivers OCTAL LATCHED TRANSCEIVER W/DU

74LVC544AD Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerNXP
Reach Compliance Codeunknown
Other featuresWITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
Control typeINDEPENDENT CONTROL
Counting directionBIDIRECTIONAL
seriesLVC/LCX/Z
JESD-30 codeR-PDSO-G24
JESD-609 codee4
length15.4 mm
Logic integrated circuit typeREGISTERED BUS TRANSCEIVER
MaximumI(ol)0.024 A
Humidity sensitivity level1
Number of digits8
Number of functions1
Number of ports2
Number of terminals24
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output characteristics3-STATE
Output polarityINVERTED
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP24,.4
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)260
power supply3.3 V
Prop。Delay @ Nom-Sup6.5 ns
propagation delay (tpd)8.5 ns
Certification statusNot Qualified
Maximum seat height2.65 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)1.2 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceNickel/Palladium/Gold (Ni/Pd/Au)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
translateN/A
width7.5 mm
Base Number Matches1
74LVC544A
Octal D-type registered transceiver; inverting; 3-state
Rev. 4 — 18 December 2012
Product data sheet
1. General description
The 74LVC544A is an octal registered inverting transceiver containing two sets of D-type
latches for temporary storage of the data flow in either direction. Separate latch enable
inputs (LEAB and LEBA) and output enable inputs (OEAB and OEBA) are provided for
each register to permit independent control of input and output in either direction of the
data flow.
The 74LVC544A contains eight D-type latches, with separate inputs and controls for each
set. For data flow from pins A to B, for example, the A to B enable input (pin EAB) must be
LOW in order to enter data from pins A0 to A7 or take data from pins B0 to B7. With
pin EAB LOW, a LOW signal on the A to B latch enable input (pin LEAB) makes the A to B
latches transparent; a subsequent LOW-to-HIGH transition on pin LEAB puts the A data
into the latches where it is stored and the B outputs no longer change with the A inputs.
With pins EAB and OEAB both LOW, the 3-state B output buffers are active and display
the data present at the outputs of the A latches.
2. Features and benefits
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low-power consumption
Direct interface with TTL levels
8-bit octal transceiver with D-type latch
Back-to-back registers for storage
Separate controls for data flow in each direction
Supports partial power-down applications; inputs/outputs are high-impedance when
V
CC
= 0 V
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from
40 C
to +85
C
and
40 C
to +125
C

74LVC544AD Related Products

74LVC544AD 74LVC544APW 74LVC544APW-T 74LVC544ADB-T 74LVC544ADB 74LVC544AD-T
Description Bus Transceivers OCTAL LATCHED TRANSCEIVER W/DU Bus Transceivers OCTAL LATCHED TRANSCEIVER W/DU Bus Transceivers OCTAL LATCHED TRANSCEIVER W/DU Bus Transceivers OCTAL LATCHED TRANSCEIVER W/DU Bus Transceivers OCTAL LATCHED TRANSCEIVER W/DU Bus Transceivers OCTAL LATCHED TRANSCEIVER W/DU
Is it Rohs certified? conform to conform to conform to conform to conform to conform to
Maker NXP NXP NXP NXP NXP NXP
Reach Compliance Code unknown unknown unknown unknown compliant unknown
Other features WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
series LVC/LCX/Z LVC/LCX/Z LVC/LCX/Z LVC/LCX/Z LVC/LCX/Z LVC/LCX/Z
JESD-30 code R-PDSO-G24 R-PDSO-G24 R-PDSO-G24 R-PDSO-G24 R-PDSO-G24 R-PDSO-G24
JESD-609 code e4 e4 e4 e4 e4 e4
length 15.4 mm 7.8 mm 7.8 mm 8.2 mm 8.2 mm 15.4 mm
Logic integrated circuit type REGISTERED BUS TRANSCEIVER REGISTERED BUS TRANSCEIVER REGISTERED BUS TRANSCEIVER REGISTERED BUS TRANSCEIVER REGISTERED BUS TRANSCEIVER REGISTERED BUS TRANSCEIVER
Humidity sensitivity level 1 1 1 1 1 1
Number of digits 8 8 8 8 8 8
Number of functions 1 1 1 1 1 1
Number of ports 2 2 2 2 2 2
Number of terminals 24 24 24 24 24 24
Maximum operating temperature 85 °C 85 °C 85 °C 85 °C 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C
Output characteristics 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE
Output polarity INVERTED INVERTED INVERTED INVERTED INVERTED INVERTED
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code SOP TSSOP TSSOP SSOP SSOP SOP
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE
Peak Reflow Temperature (Celsius) 260 260 260 260 260 260
propagation delay (tpd) 8.5 ns 8.5 ns 8.5 ns 8.5 ns 8.5 ns 8.5 ns
Certification status Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
Maximum seat height 2.65 mm 1.1 mm 1.1 mm 2 mm 2 mm 2.65 mm
Maximum supply voltage (Vsup) 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V
Minimum supply voltage (Vsup) 1.2 V 1.2 V 1.2 V 1.2 V 1.2 V 1.2 V
Nominal supply voltage (Vsup) 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
surface mount YES YES YES YES YES YES
technology CMOS CMOS CMOS CMOS CMOS CMOS
Temperature level INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL
Terminal surface Nickel/Palladium/Gold (Ni/Pd/Au) Nickel/Palladium/Gold (Ni/Pd/Au) NICKEL PALLADIUM GOLD NICKEL PALLADIUM GOLD Nickel/Palladium/Gold (Ni/Pd/Au) NICKEL PALLADIUM GOLD
Terminal form GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING
Terminal pitch 1.27 mm 0.65 mm 0.65 mm 0.65 mm 0.65 mm 1.27 mm
Terminal location DUAL DUAL DUAL DUAL DUAL DUAL
Maximum time at peak reflow temperature 30 30 30 30 30 30
width 7.5 mm 4.4 mm 4.4 mm 5.3 mm 5.3 mm 7.5 mm
Base Number Matches 1 1 1 1 1 1
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