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FDR856P

Description
P-Channel Logic Level Enhancement Mode Field Effect Transistor
CategoryDiscrete semiconductor    The transistor   
File Size216KB,8 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
Environmental Compliance
Download Datasheet Parametric View All

FDR856P Overview

P-Channel Logic Level Enhancement Mode Field Effect Transistor

FDR856P Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerFairchild
Parts packaging codeSOT
package instructionSMALL OUTLINE, R-PDSO-G8
Contacts8
Reach Compliance Codeunknow
ECCN codeEAR99
Other featuresLOGIC LEVEL COMPATIBLE
ConfigurationSINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage30 V
Maximum drain current (Abs) (ID)5.1 A
Maximum drain current (ID)5.1 A
Maximum drain-source on-resistance0.025 Ω
FET technologyMETAL-OXIDE SEMICONDUCTOR
JESD-30 codeR-PDSO-G8
JESD-609 codee3
Humidity sensitivity level1
Number of components1
Number of terminals8
Operating modeENHANCEMENT MODE
Maximum operating temperature150 °C
Package body materialPLASTIC/EPOXY
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Polarity/channel typeP-CHANNEL
Maximum power dissipation(Abs)1.8 W
Certification statusNot Qualified
surface mountYES
Terminal surfaceMatte Tin (Sn)
Terminal formGULL WING
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
transistor applicationsSWITCHING
Transistor component materialsSILICON
March 1998
FDR856P
P-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
SuperSOT
TM
-8 P-Channel enhancement mode power field
effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very
high density process is especially tailored to minimize
on-state resistance and provide superior switching
performance. These devices are particularly suited for low
voltage applications such as battery powered circuits or
portable electronics where low in-line power loss, fast
switching and resistance to transients are needed.
Features
- 6.3 A, -30 V, R
DS(ON)
=0.025
@ V
GS
= -10 V
R
DS(ON)
=0.040
@ V
GS
= -4.5 V.
SuperSOT
TM
-8 package:
small footprint (40% less than SO-8);low profile (1mm
thick);maximum power comperable to SO-8.
High density cell design for extremely low R
DS(ON)
.
SOT-23
SuperSOT -6
TM
SuperSOT
TM
-8
SO-8
SOT-223
SOIC-16
D
D
S
S
85
6P
G
5
6
4
3
2
1
pin
1
SuperSOT
TM
-8
D
D
D
7
8
Absolute Maximum Ratings
Symbol
V
DSS
V
GSS
I
D
P
D
Parameter
Drain-Source Voltage
T
A
= 25
o
C unless other wise noted
FDR856P
-30
±20
(Note 1a)
Units
V
V
A
Gate-Source Voltage - Continuous
Maximum Drain Current - Continuous
- Pulsed
Maximum Power Dissipation
(Note 1a)
(Note 1b)
(Note 1c)
-5.1
-50
1.8
1
0.9
-55 to 150
W
T
J
,T
STG
R
θ
JA
R
θ
JC
Operating and Storage Temperature Range
°C
THERMAL CHARACTERISTICS
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
50
25
°C/W
°C/W
© 1998 Fairchild Semiconductor Corporation
FDR856P Rev.B

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