Learn about CTSD's precision ADC technology in an unconventional way!

Table 1. Clock edge sampling

This is due to the effect of the ADC input on the instantaneous error seen by the amplifier; that is, the ADC's influence can be determined even before feedback is received, which is undesirable. If the ADC affects the accumulated average error data so that the error due to the 1-clock-cycle delayed feedback reaches the average, the system's output will be limited.

The integrator is the analog equivalent of an averaging accumulator. The loop gain remains high, but only at low frequencies, or within the frequency bandwidth of interest. This ensures that the ADC is not subject to any transient errors that could lead to a runaway situation. Therefore, the amplifier in the loop is now replaced by an integrator followed by the ADC and DAC, as shown in Figure 3a.

Figure 3. (a) Introducing the integrator into the loop. (b) Rearranging the loop to focus on DOUTADC _as the output.

The target component here is DOUTADC _. Let's rearrange the loop components, focusing on _DOUTADC as the system's output, as shown in Figure 3b. Next, let's consider simplifying the DAC and Rf paths. To do this, let's first delve deeper into the DAC. The DAC's role is to convert the DIN _digital signal into an equivalent analog current or voltage proportional to the reference voltage. To further leverage the benefits of a continuous voltage reference, we consider a common DAC architecture based on a resistor ladder, which presents no switching load to the reference. Considering a temperature-sensing resistor DAC, it converts DIN into a DAC current according to Equation ₅ .

Where V _REF = V _REFP – V _REFM , which is the total reference voltage of the DAC.

• D _IN = Digital input in the temperature measurement code

• Rf = feedback _resistor ; broken down into unit components

• N = number of digits

Figure 4. General-purpose temperature-sensing resistor DAC.

To obtain a voltage output, an operational amplifier in a transimpedance configuration is used for I to V conversion, as shown in Figure 4. Therefore,

Returning to the discrete loop in Figure 3b, this V _OUTDAC is again converted back into current I _fb through the feedback resistor of the inverting amplifier . That is, the signal flow is I _DAC → V _{OUTDA C} → I _fb . This can be expressed mathematically as:

From the signal flow and equations above, we can see that converting _VOUTDAC to Ifb _is a redundant step that can be bypassed. Removing the redundant components and, for simplicity, expressing (VREFP _– VREFM ₎ as VREF _, we can redraw the loop as shown in Figure 5.

Figure 5. Removing the redundant I-to-V conversion section and feedback resistors.

Voila! We have built a first order Σ-Δ loop! We put together all the known components: the inverting amplifier, the ADC, and the DAC.

Now that we've mastered the construction of the CTSD loop, we haven't yet appreciated the unique aspects of this particular loop. Let's first understand oversampling. ADC data is only useful if there are enough sampled and digitized data points to extract or interpret the analog signal information. The Nyquist criterion suggests that to faithfully reconstruct the input signal, the ADC sampling frequency should be at least twice the signal frequency. Adding more data points beyond this minimum requirement will further reduce interpretation errors. Following this principle, choosing a sampling frequency much higher than the recommended Nyquist frequency in a sigma-delta calculation is called oversampling. Oversampling spreads the overall noise across a higher frequency range, helping to reduce quantization noise in the frequency band of interest, as shown in Figure 6.

Figure 6. Noise spectral density comparison between Nyquist sampling and oversampling.

Signal chain designers should not be confused when sigma-delta experts use terms such as noise transfer function (NTF) or noise shaping; our next step will help them gain an intuitive understanding of these terms specific to sigma-delta converters. Let’s review a simple inverting amplifier configuration and the error Q _e generated at the amplifier output , as shown in Figure 7.

Figure 7. Error generation in an inverting amplifier configuration.

The contribution of this error at the output can be quantified as

From the mathematical formula, we can see that the error Qe _is attenuated by the open-loop gain of the amplifier, which again shows the advantage of closed loop.

This understanding of the advantages of closed-loop can be extended to the quantization error, Q _e , of the ADC in the CTSD loop. This error is caused by the digitization of the continuous signal at the integrator output, as shown in Figure 8 .

_{Figure 8. Quantization error Q e} generated in the sigma-delta loop .

We can now intuitively conclude that this Q _e can be attenuated by an integrator. The integrator TF is |H _INTEG (f)| = 1/|s × RC| = 1/2πfRC, and its corresponding frequency domain representation is shown in Figure 9. Its curve is equivalent to that of a low-pass filter with high gain at low frequencies, and the gain decreases linearly with increasing frequency. Accordingly, the attenuation of Q _{e behaves similarly to that of a high-pass filter.}

Figure 9. Integrator transfer function.

The mathematical representation of this attenuation factor is the noise transfer function. Let's temporarily ignore the sampler in the ADC and the switches in the DAC. The NTF, VOUTADC _/ Qe _, can be evaluated in the same manner as for the inverting amplifier configuration. Its frequency-domain curve resembles that of a high-pass filter, as shown in Figure 10.

In the target frequency band, the quantization noise is completely attenuated and pushed to high frequencies where it is "irrelevant to us." This is called noise shaping.

Figure 10. Noise transfer function without a sampler—with high-pass filter curve.

The quantization noise shaping analogy remains unchanged due to the presence of a sampler in the loop. However, the NTF frequency response will replicate the image at every multiple of f _S , as shown in Figure 10, resulting in notches at every integer multiple of the sampling frequency.

Figure 11. Noise transfer function of the CTSD ADC.

The uniqueness of the sigma-delta architecture is that it places an integrator and a DAC loop around a raw ADC (for example, a 4-bit ADC), significantly reducing the quantization noise in the target frequency bandwidth through oversampling and noise shaping, turning this raw ADC into a 16-bit or 24-bit precision ADC.

These basic principles of first-order CTSD ADCs can now be extended to modulator loops of any order. The sampling frequency, raw ADC specifications, and loop order are the primary design decisions driven by the ADC performance requirements.

Typically, in an ADC signal chain, digitized data is post-processed by an external digital controller to extract any signal information. As we now know, in a sigma-delta architecture, the signal is oversampled. If this oversampled digital data were provided directly to an external controller, a significant amount of redundant data would need to be processed. This would result in excessive power and board space costs in the digital controller design. Therefore, before providing the data to the digital controller, it should be effectively downsampled without sacrificing performance. This process is called decimation and is performed by a digital decimation filter. Figure 11 shows a typical CTSD modulator with an on-chip digital decimation filter.

Figure 12. (a) Block diagram of the CTSD ADC modulator loop from analog input to digital output. (b) Spectral representation of the input signal at the modulator output and the digital filter output.

Figure 12b shows the frequency response of an in-band analog input signal. At the modulator output, we see that the quantization noise is significantly reduced within the frequency band of interest after noise shaping. The digital filter helps attenuate the shaped noise outside this frequency bandwidth of interest, so that the final digital output, DOUT, is at the Nyquist sampling rate.

Now that we know how the CTSD ADC maintains the continuous integrity of the input signal, this greatly simplifies the signal chain design. This architecture does have some limitations, primarily dealing with the sampling clock, MCLK. The CTSD modulator loop operates by accumulating the error current between I _IN and I _DAC . Any error in this integrated value causes the ADC in the loop to sample this error and reflect it at the output. For our first-order integrator loop, the integrated value over the T _s sampling period of constant I _IN and I _{DAC is expressed as}

For 0 input, the parameters that affect this integral error include

• MCLK frequency: As shown in Equation 10, if the MCLK frequency is scaled, the RC coefficient that controls the integral slope also needs to be readjusted to obtain the same integral value. This means that the CTSD modulator is tuned for a fixed MCLK clock frequency and cannot support a varying MCLK.

• MCLK jitter: The DAC code and I _DAC change every clock period, T _s . If the I _DAC period changes randomly, the average integrated value will vary, as shown in Figure 13. Therefore, any error in the form of jitter in the sampling clock period will affect the performance of the modulator loop.

Figure 13. Clock sensitivity of the CTSD modulator.

For the reasons mentioned above, CTSD ADCs are sensitive to MCLK frequency and jitter. However, ADI has found ways to address these errors. For example, the challenge of generating an accurate, low-jitter MCLK and delivering it to the ADC in the system can be addressed by using a low-cost, local crystal oscillator close to the ADC. Errors around the fixed sampling frequency are addressed through the use of an innovative asynchronous sample rate converter (ASRC), which provides an independently variable digital output data rate to the digital controller without regard for the fixed sampling MCLK. Further details on this will be provided in subsequent articles in this series.

This article focuses on the insights gained from using the closed-loop op amp configuration concept to build the modulator loop from steps 1 to 6. Figure 11a also helps us see these advantages.

The CTSD ADC's input impedance is identical to that of the inverting amplifier—resistive and easy to drive. Innovative techniques have been employed to make the reference voltage used by the modulator loop's DAC also resistive. The ADC's sampler is placed after the integrator, rather than directly at the input, achieving inherent aliasing rejection of interferers outside the band of interest.