Analog Tips - ADC Decimation
Wideband GSPS analog-to-digital converters (ADCs) offer numerous performance advantages for high-speed acquisition systems. These ADCs provide visibility across a wide frequency spectrum. However, while some applications require a wideband front end, others require the ability to filter and tune to a narrower frequency spectrum.
Decimation is a method of observing only the periodic portion of the ADC's samples and ignoring the rest. The result of decimation is a reduction in the ADC's sampling rate. For example, a 1/4 decimation mode means (total number of samples)/4, effectively discarding all other samples.
The ADC must also include a numerically controlled oscillator (NCO) and a filtering and mixing element (serving as a companion to the decimation function). Digital filtering effectively removes out-of-band noise within a narrow bandwidth set by the decimation rate. The digital tuning word of the NCO, acting as a local oscillator, provides fractional division of the sampling rate, providing precise positioning by the number of bits of resolution. The tuning word has the range and resolution to place the filter where it is needed spectrally.
The filter passband should match the effective spectral width of the converter after decimation. A significant advantage of using a DDC is the ability to locate the harmonics of the fundamental signal so that they fall outside the frequency band of interest.
The DDC filter's digital filtering removes noise outside a narrow bandwidth. The ideal ADC's SNR calculation must account for the processing gain of the filtered noise . With a perfect digital filter, the processing gain from filtering the noise increases by 3dB for every power-of-two reduction in bandwidth.
Ideal SNR (including processing gain) =
6.02 × N + 1.76 dB + 10log 10 (f s /(2 × BW))
Figure 1. Using a lowpass filter and an NCO to perform frequency translation implements a bandpass filter. Frequency planning ensures that unwanted harmonics and spurs fall outside the bandwidth.
AD9694
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JESD204B (Subclass 1) encoded serial digital output
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Lane rates up to 15 Gbps
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Total power consumption: 1.66 W (500 MSPS)
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Each analog-to-digital converter (ADC) channel: 415 mW
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SFDR: 82 dBFS (305 MHz, 1.80 V pp input range)
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SNR: 66.8 dBFS (305 MHz, 1.80 V pp input range)
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Noise density: −151.5 dBFS/Hz (1.80 V pp input range)
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DC power supplies: 0.975 V, 1.8 V, and 2.5 V
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No missing codes
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ADC internal reference voltage source
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Analog input buffer
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On-chip dithering to improve small signal linearity
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Flexible differential input range
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1.44 pp to 2.16 V pp (1.80 V pp nominal)
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Analog input full power bandwidth: 1.4 GHz
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Amplitude detection bits support efficient AGC
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Integrated 4 broadband digital processors
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48-bit NCO, up to 4 cascaded half-band filters
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Differential clock input
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Integer clock divider values: 1, 2, 4, or 8
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On-chip temperature diode
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Flexible JESD204B channel configuration















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