VLSI CADII-Design

A modern VLSI chip is a remarkably complex beast:  billions of transistors, millions of logic gates deployed for computation and control, big blocks of memory, embedded blocks of pre-designed functions designed by third parties (called “intellectual property” or IP blocks).  How do people manage to design these complicated chips?  Answer:  a sequence of computer aided design (CAD) tools takes an abstract description of the chip, and refines it step-wise to a final design. This class focuses on the major design tools used in the creation of an Application Specific Integrated Circuit (ASIC) or System on Chip (SoC) design.  Our focus in this part of the course is on the key logical and geometric representations that make it possible to map from logic to layout, and in particular, to place, route, and evaluate the timing of large logic networks. Our goal is for students to understand how the tools themselves work, at the level of their fundamental algorithms and data structures. Topics covered will include: technology mapping, timing analysis, and ASIC placement and routing.

Recommended Background:

Programming experience (C, C++, Java, Python, etc.) and basic knowledge of data structures and algorithms (especially recursive algorithms).  An understanding of basic digital design:  Boolean algebra, Kmaps, gates and flip flops, finite state machine design.  Linear algebra and calculus at the level of a junior or senior in engineering.  Elementary knowledge of RC linear circuits (at the level of an introductory physics class).

How do people design these complex chips? Answer: A series of computer-aided design (CAD) tools provide an abstract description of the chip and gradually refine it to the final design. This course focuses on the main design tools used when building application-specific integrated circuit (ASIC) or system-on-chip (SoC) designs.

• Chapter 1：Welcome and Introduction (19 minutes and 17 seconds)

• Chapter 2：Two Tools Tutorial (4 minutes and 2 seconds)

• Chapter 3：Basics (17 minutes and 29 seconds)

• Chapter 4：Wirelength Estimation (15 minutes and 5 seconds)

• Chapter 5：Simple Iterative Improvement Placement (12 minutes and 18 seconds)

• Chapter 6：Iterative Improvement with Hill Climbing (15 minutes and 16 seconds)

• Chapter 7：Simulated Annealing Placement (27 minutes and 3 seconds)

• Chapter 8：Analytical Placement_ Quadratic Wirelength Model (14 minutes and 39 seconds)

• Chapter 9：Analytical Placement_ Quadratic Placement (26 minutes and 40 seconds)

• Chapter 10：Analytical Placement_ Recursive Partitioning (18 minutes and 15 seconds)

• Chapter 11：Analytical Placement_ Recursive Partitioning Example (16 minutes and 28 seconds)

• Chapter 12：Technology Mapping Basics (19 minutes and 13 seconds)

• Chapter 13：Technology Mapping as Tree Covering (29 minutes and 36 seconds)

• Chapter 14：Technology Mapping—Tree-ifying the Netlist (13 minutes and 46 seconds)

• Chapter 15：Technology Mapping—Recursive Matching (9 minutes and 0 seconds)

• Chapter 16：Technology Mapping—Minimum Cost Covering (16 minutes and 8 seconds)

• Chapter 17：Technology Mapping—Detailed Covering Example (14 minutes and 28 seconds)

• Chapter 18：Routing Basics (17 minutes and 13 seconds)

• Chapter 19：Maze Routing_ 2-Point Nets in 1 Layer (16 minutes and 35 seconds)

• Chapter 20：Maze Routing_ Multi-Point Nets (12 minutes and 24 seconds)

• Chapter 21：Maze Routing_ Multi-Layer Routin (12 minutes and 21 seconds)

• Chapter 22：Maze Routing_ Non-Uniform Grid Costs (14 minutes and 57 seconds)

• Chapter 23：Implementation Mechanics_ How Expansion Works (23 minutes and 32 seconds)

• Chapter 24：Implementation Mechanics_ Data Structures & Constraints (18 minutes and 2 seconds)

• Chapter 25：Implementation Mechanics_ Depth First Search (14 minutes and 6 seconds)

• Chapter 26：From Detailed Routing to Global Routing (15 minutes and 48 seconds)

• Chapter 27：Basics (7 minutes and 13 seconds)

• Chapter 28：Logic-Level Timing_ Basic Assumptions & Models (30 minutes and 59 seconds)

• Chapter 29：Logic-Level Timing_ STA Delay Graph, ATs, RATs, and Slacks (27 minutes and 30 seconds)

• Chapter 30：Logic-Level Timing_ A Detailed Example and the Role of Slack (10 minutes and 2 seconds)

• Chapter 31：Logic-Level Timing_ Computing ATs, RATs, Slacks, and Worst Paths (26 minutes and 55 seconds)

• Chapter 32：Interconnect Timing_ Electrical Models of Wire Delay (16 minutes and 6 seconds)

• Chapter 33：Interconnect Timing_ The Elmore Delay Model (14 minutes and 19 seconds)

• Chapter 34：Interconnect Timing_ Elmore Delay Examples (14 minutes and 56 seconds)