The circuit shown in Figure 1 uses an ADF4350 frequency synthesizer with an integrated VCO and an external PLL , minimizing spurious output by isolating the PLL frequency synthesizer circuit from the VCO circuit.

Devices that integrate PLL and VCO can feed through the digital PLL circuit to the VCO, which results in higher spurious levels due to the close proximity of the PLL circuit to the VCO.

The circuit shown in Figure 1 uses a fully integrated fractional-N PLL and the VCOADF4350, which when used with the ADF4153 PLL can generate frequencies in the 137.5MHz to 4400MHz range.

In addition to spurious performance improvements, another potential advantage of using an external PLL is increased frequency resolution. For example, if the ADF4157 PLL is chosen instead of the ADF4153, the frequency resolution of the PLL can be as fine as 0.7Hz.

The ADF4350 is a wideband PLL and VCO consisting of three independent multi-band VCOs. Each VCO covers a range of approximately 700 MHz (with some overlap between VCO frequencies). This provides a basic VCO frequency range of 2.2GHz to 4.4GHz. Frequencies below 2.2 GHz can be generated using the DF4350's internal frequency divider.

For most applications, the ADF4350's internal PLL is used to lock the VCO. In addition to locking the PLL, another important function of the PLL circuit is VCO band selection, which uses the internal reference (R) and feedback (N) counters of the internal PLL to compare the VCO output and the reference input. To complete frequency generation, the internal PLL must be enabled and the desired frequency must be set. Once sufficient time has elapsed for band selection, the internal PLL can be disabled, and finally, the external PLL can be enabled. The external PLL compares the reference frequency with the VCO output frequency to generate a stable DC voltage to lock the PLL.

Figure 2 shows the output frequency spur measured at RFOUTA+ using the ADF4350 internal PLL and VCO, with the ADF4153 PLL disabled. Note that there are PFD spurs at 13 MHz and 26 MHz.

Figure 3 shows the measured output spurs at RFOUTA+ when the ADF4350 internal PLL circuit is disabled and the external ADF4153 PLL is active. In this mode, the charge pump output of the ADF4153 drives the loop filter, which in turn drives the V _TUNE input of the ADF4350. The V _TUNE input controls the ADF4350 VCO output frequency.

Comparing Figures 2 and 3, it can be seen that the spurs generated by the phase frequency detector (PFD) frequency (at 13 MHz and 26 MHz) in Figure 2 disappear into the noise floor in Figure 3.