The RF transmitters in Figures 1 and 2 use the AD9142A TxDAC, a wideband I/Q modulator with integrated ADRF6720 phase-locked loop (PLL)/voltage-controlled oscillator (VCO), and the ADL5320 ¼ W driver amplifier.

Signal bias and trim in the DAC-to-modulator interface circuit are controlled by four ground-referenced resistors (RBI+, RBI−, RBQ+, RBQ−) and two shunt resistors (RLI, RLQ). Input and output matching of the ADL5320 driver amplifier is achieved by shunt capacitors at the input and output. See the ADL5320 data sheet for required matching components and locations.

Figure 1. Simplified circuit diagram of I/Q modulator with integrated DAC and driver amplifier (all connections and decoupling not shown)


Figure 2. The AD9142A evaluation board and ADRF6720 evaluation board are modified to implement this circuit.

The nominal and default values ​​of the AD9142A full-scale output current are 20 mA. With four 50 Ω resistors referenced to ground (RBI+ = RBI− = RBQ+ = RBQ−), this current produces a 500 mV DC bias level and 2 V pp differential full-scale on each DAC output pair Output voltage swing. The 2 V pp voltage swing can be adjusted with the RL shunt resistor (RL = RLI = RLQ), which is placed in parallel with the 500 Ω I/Q input impedance of the ADRF6720 modulator. The 500 mV DC bias level is not affected by this adjustment. For example, if the load is 100 Ω differential rms, each single-ended output will swing from 250 mV to 750 mV but still maintain a 500 mV average.

Figure 3 shows the resulting pp differential swing as a function of the RL swing-limiting resistor and the 500 Ω parallel differential input impedance.


Figure 3. Effective AC limiting resistor versus peak-to-peak voltage swing using 50 Ω bias setting resistor.

I/Q filtering
It is necessary to place an anti-aliasing filter between the DAC and the modulator to filter out Nyquist image, common mode noise, and wideband DAC noise. The filter should be placed between the DC bias setting resistor,

which sets the filter source impedance, and the AC limiter resistor, which sets the filter load impedance.


Figure 4. Recommended DAC modulator interface topology (fC = 300 MHz, fifth-order Butterworth filter)

System Level Simulation
Figure 5 shows the simulated cascade performance of the I/Q modulator and driver amplifier at 2140 MHz. The dynamic range and gain of the AD9142A, ADRF6720, and ADL5320 are well matched. Figure 5 shows the composite output third-order intercept point (OIP3) of 39.4 dBm and adjacent channel leakage ratio (ACLR) performance of approximately −76 dBc. This simulation is completed using ADIsimRF Design Tool .

The linearity of the ADRF6720 can be optimized through the MOD_RSEL (Register 0x31, Bits[12:6]) and MOD_CSEL (Register 0x31, Bits[5:0]) settings. These settings control the amount of inversion distortion in the baseband input stage, which corrects the distortion.

Figures 6 to 11 show the measured output second-order intercept point (OIP2) and OIP3 curves (optimized at zero IF, 100 MHz and 200 MHz complex IF) after adjusting the MOD_RSEL register and MOD_CSEL register of the ADRF6720.

Figure 6, Figure 7 and Figure 8 show optimized OIP3 performance every 32 steps on the MOD_RSEL axis; OIP3 performance has no obvious function relationship with MOD_CSEL at zero IF. However, the sensitivity of MOD_CSEL is higher at higher IF frequencies.

By optimizing MOD_RSEL and MOD_CSEL, OIP3 is approximately 42 dBm at zero IF, approximately 45 dBm at 100 MHz IF, and approximately 48 dBm at 200 MHz IF.

RSEL and CSEL adjustments do not have a large impact on OIP2 performance; however, there is some performance degradation at mid-range frequencies.


Figure 5. ADIsimRF design tool screenshot showing cascaded performance of AD9142A, ADRF6720, and ADL5320


Figure 6. OIP3 versus MOD_CSEL and MOD_RSEL (fRF = 2140 MHz, zero IF, ADL5320 output power 11 dBm)


Figure 7. OIP3 versus MOD_CSEL and MOD_RSEL (fRF = 2140 MHz, 100 MHz IF, 2340 MHz LO, ADL5320 output power 11 dBm)


Figure 8. OIP3 versus MOD_CSEL and MOD_RSEL (fRF = 2140 MHz, 200 MHz IF, 2340 MHz LO, ADL5320 output power 11 dBm)


Figure 9. OIP2 versus MOD_CSEL and MOD_RSEL (fRF = 2140 MHz, zero IF, ADL5320 output power 11 dBm)


Figure 10. OIP2 versus MOD_CSEL and MOD_RSEL (fRF = 2140 MHz, 100 MHz IF, 2340 MHz LO, ADL5320 output power 11 dBm)


Figure 11. OIP2 versus MOD_CSEL and MOD_RSEL (fRF = 2140 MHz, 200 MHz IF, 2340 MHz LO, ADL5320 output power 11 dBm)

Selecting the Output Power Level
Although the output power level of this circuit can be as high as 12 dBm, Operation at this level is impractical, especially if the modulating carrier has a high peak-to-average ratio. In order to obtain acceptable distortion levels, a significant setback is required. Adjacent channel power ratio (ACPR) has become a mainstream indicator for evaluating system-level distortion.

Figures 12 and 13 show ACPR measured at the output of the ADL5320 versus output power; they are three IF cases using single-carrier WCDMA (Test Model 1-64) and LTE (Test Model 1_1 64QAM) respectively. The system achieves ACPR of approximately −75 dB to −80 dB over the −2 dBm to +6 dBm output power range. In the case of LTE signals, ACPR is defined as the ratio of the power in the carrier (bandwidth of 4.515 MHz) to the power in the adjacent channel (channel spacing of 5 MHz), also measured at a bandwidth of 4.515 MHz.


Figure 12. ADL5320 amplifier output ACLR versus output power (zero IF, optimized RSEL and CSEL on ADRF6720 at 2140 MHz, 1C WCDMA TM1-64)


Figure 13. ACLR at the ADL5320 amplifier output vs. output power (optimized RSEL and CSEL OIP3 on ADRF6720, 1C LTE TM1_1 64QAM)

OIP2 and OIP3 can be improved by adjusting MOD_RSEL and MOD_CSEL mentioned above; accordingly, ACPR The improvements are shown in Figures 13 and 14. This improvement is more pronounced at higher output power levels.


Figure 14. ADL5320 amplifier output ACLR versus output power (zero IF, RSEL and CSEL on optimized and unoptimized ADRF6720 at 2140 MHz, 1C WCDMA TM1-64)


Figure 15. The relationship between ACLR and output power at the output end of the ADL5320 amplifier (zero IF, RSEL and CSEL on optimized and unoptimized ADRF6720 at 2140 MHz, 1C LTE TM1_1 64QAM).

The spectrum curves of a single WCDMA and LTE at 2140 MHz are shown in Figure 16. and shown in Figure 17.


Figure 16. Adjacent Channel Power Performance at ADL5320 Amplifier Output (Zero IF, Optimized RSEL and CSEL on ADRF6720 at 2140 MHz, 1C WCDMA TM1-64)


Figure 17. Adjacent channel power performance at ADL5320 amplifier output (zero IF, RSEL and CSEL on optimized ADRF6720 at 2140 MHz, 1C LTE TM1_1 64QAM)

PCB Layout Recommendations
Special attention should be paid to the layout of the DAC/modulator/amplifier interface. PCB layout recommendations are as follows:

Keep all I/Q differential trace lengths well matched.
Place the filter termination resistor as close as possible to the modulator input.
Place the DAC output 50 Ω resistor as close to the DAC as possible.
Widen the traces past the filter network to reduce signal loss.
Place vias around all DAC output traces, filter networks, modulator output traces, LO input traces, amplifier input traces, and amplifier output traces.
Route the LO and modulator output traces on different layers or at a 90° angle to each other to prevent coupling.