The circuit shown in Figure 1 is a 65 MHz bandwidth receiver front end based on the ADL5565 ultra-high dynamic range differential amplifier driver and the AD6657A 11-bit, 200 MSPS quad IF receiver .

Fourth-order Butterworth anti-aliasing filters are optimized based on the performance and interface requirements of the amplifier and IF receiver. The total insertion loss caused by the filter network and other resistive components is only 2.0 dB. The overall circuit bandwidth is 65 MHz, and the low-pass filter has a 1 dB bandwidth at 190 MHz and a 3 dB bandwidth at 210 MHz. Passband flatness is 1dB.

This circuit is optimized for processing 65 MHz bandwidth IF signals centered at 140 MHz and sampled at 184.32 MSPS. The measured SNR and SFDR using a 140 MHz analog input in the 65 MHz band were 70.1 dBFS and 80.9 dBc, respectively.

The circuit shown in Figure 1 accepts a single-ended input and converts it to a differential signal using a wide-bandwidth (3 GHz) M/A-COM ECT1-1-13M 1:1 transformer. The ADL5565 6.0 GHz differential amplifier has a differential input impedance of 200 Ω when operating at 6 dB gain, 100 Ω when operating at 12 dB gain, and 67 Ω when operating at 15.5 dB gain.

The ADL5565 is an ideal driver for the AD6657A . A low-pass filter enables a fully differential architecture in the ADC, providing good high-frequency common-mode rejection while minimizing second-order distortion products. The ADL5565 provides 6 dB, 12 dB, and 15.5 dB gain depending on the input connection. In this circuit, a 6 dB gain is used to compensate for the insertion loss of the filter network and transformer (approximately 2.1 dB), providing a total signal gain of 4.0 dB. Gain also helps minimize the noise effects of the amplifier.

The AD6657A is a quad-channel IF receiver in which each ADC output is internally connected to a digital noise shaping requantizer (NSR) block. Integrated NSR circuitry improves signal-to-noise ratio (SNR) performance at smaller frequency bands within the Nyquist bandwidth.

The NSR module can be programmed to provide bandwidth at 22%, 33%, or 36% of the sample rate. For the data used in this circuit note, the sampling rate is 184.32 MSPS and the following NSR settings apply:

• NSR bandwidth = 36%
• Tuning Word (TW) = 12
• Left band edge = 11.06 MHz (input = 173.26 MHz)
• Center frequency = 44.24 MHz (input = 140.08 MHz)
• Right band edge = 77.41 MHz (input = 106.91 MHz)

Please refer to the AD6657A data sheet for the detailed working principle of the NSR module.

The anti-aliasing filter is a fourth-order Butterworth low-pass filter designed using a standard filter design program ( Agilent ADS in this case). The Butterworth filter was chosen because of its flat response. The fourth-order filter produces an AC-to-noise-to-bandwidth ratio of 1.03. Other filter design programs are available from Nuhertz Technologies or Quite Universal Circuit Simulator (Qucs) Simulation.

For optimal performance, the ADL5565 should be loaded with a net differential load of at least 200 Ω. The 20 Ω series resistor isolates the filter capacitor from the amplifier output, resulting in a net load impedance of 249 Ω when the downstream impedance is added.

A 15 Ω resistor in series with the ADC input isolates internal switching transients from the filter and amplifier. The 110 Ω resistor is placed in parallel with the ADC to lower the input impedance of the ADC, making performance more predictable.

The differential input impedance of the AD6657A is approximately 2.4 kΩ in parallel with 2.2 pF. For this type of switched capacitor input ADC, the real and imaginary parts are a function of the input frequency; see application note AN-742 for detailed analysis .

The fourth-order Butterworth filter is designed with a source impedance of 50 Ω, a load impedance of 209 Ω, and a 3 dB bandwidth of 190 MHz. The final circuit values ​​of the filter are shown in Figure 1. The values ​​generated from the filter program are shown in Figure 2. The values ​​chosen for the filter passive components are the closest standard values ​​to the program-generated values. The ADC's internal 2.2 pF capacitor serves as the final shunt capacitor for the filter design.

As can be seen from this design, achieving optimal performance can sometimes be an iterative process. The filter programmed values ​​are very close to the final values, but due to some board parasitic capacitance the final filter values ​​are slightly different. Figure 3 shows the final design values ​​of the filter.

Table 1 summarizes the measured performance of the system with a 3 dB bandwidth of 210 MHz. The total insertion loss of the network is approximately 2 dB. Figure 4 shows the bandwidth response of the final filter circuit, and Figure 5 shows the SNR and SFDR performance.

Filter and interface design program

This section introduces common methods for amplifier/ADC and filter interface design. In order to achieve optimal performance (bandwidth, SNR, SFDR, etc.), the amplifier and ADC should impose certain design constraints on the general circuit:

1. Amplifiers should refer to the correct DC loading recommended by the data sheet for optimal performance.
2. The correct number of series resistors must be used between the amplifier and filter loads. This is to prevent unwanted signal spikes within the passband.
3. The input to the ADC should be reduced with an external shunt resistor and the correct series resistor used to isolate the ADC from the filter. This series resistor will also reduce signal spikes.

This design approach tends to take advantage of the relatively high input impedance of most high-speed ADCs and the relatively low impedance of the driving source to minimize the insertion loss of the filter.

For details on the design procedure, see Circuit Notes CN-0227 and CN-0238 .

Circuit Optimization Techniques and Tradeoffs

The parameters within this interface circuit are highly interactive; therefore optimizing all critical specifications of the circuit (bandwidth, bandwidth flatness, SNR, SFDR, gain, etc.) is nearly impossible. However, by varying RA _and RKB _, the signal spikes that typically occur within the bandwidth response can be minimized.

_{The series resistor (R KB} ) at the ADC input should be chosen to minimize distortion caused by any residual charge injection (from the internal sampling capacitance of the ADC). Increasing this resistance also tends to reduce signal spikes within the band.

However, increasing R _KB increases signal attenuation, so the amplifier must drive a larger signal to fill the ADC's input range.

Another way to optimize passband flatness is to slightly change the filter shunt capacitance.

The ADC input termination resistor (2R _TADC ) should generally be selected such that the net ADC input impedance is between 200 Ω and 400 Ω. Lowering this resistor reduces the effect of the ADC input capacitance and stabilizes the filter design, but it increases the circuit's insertion loss. Increasing this value will also reduce signal spikes.

The trade-offs between the above factors can be somewhat difficult. In this design, each parameter is equally weighted; therefore, the values ​​selected represent the interface performance for all design features. In some designs, different values ​​can be selected to optimize SFDR, SNR, or input drive levels based on system requirements.

The SFDR performance in this design depends on two factors: amplifier and ADC interface component values, as shown in Figure 1. The final SFDR performance numbers shown in Table 1 and Figure 5 are obtained after optimizing the filter design, taking into account the board parasitic capacitance and non-ideal components used in the filter design.

Another factor that can be weighed in this particular design is the ADC full-scale setting. For the data obtained with this design, the full-scale ADC differential input voltage was set to 1.75 V pp, which optimizes SFDR. Changing the full-scale input range to 2.0 V pp slightly improves SNR, but the SFDR performance is slightly degraded. Changing the full-scale input range in the opposite direction to 1.5 V pp slightly improves SFDR, but SNR performance is slightly degraded.

Note that the signal in this design is ac-coupled with a 0.1 µF capacitor to block the common-mode voltage between the amplifier, its termination resistor, and the ADC input. See the AD6657A data sheet for details on common-mode voltages.

Passive Components and PCB Parasitic Considerations

The performance of this or any high-speed circuit is highly dependent on proper PCB layout, including but not limited to power supply bypassing, controlled impedance lines (if required), component placement, signal routing, and power and ground planes. Details of high-speed ADC and amplifier PCB layout can be found in the tutorial ">MT-031 and MT-101 .

For passive components within the filter, use low parasitic surface mount capacitors, inductors, and resistors. The inductor chosen is from the Coilcraft 0603CS series. The stability and accuracy of the surface mount capacitors used in the filter are 5%, C0G, type 0402.

Complete documentation for the system is available in the CN-0259 Design Support Package ( CN0259-DesignSupport ).