fish001

Evaluation board for ISOSD61L isolated sigma-delta converter

EVALST-ISOSD61L

 
Overview

The EVALST-ISOSD61L is a full-featured evaluation board designed to allow the user to evaluate all the features of the ISOSD61L isolated analog-to-digital converter (ADC).

The ISOSD61L device is a 1-bit sigma-delta modulator with an output buffer separated from the input interface circuitry by a galvanic isolation barrier. The isolation barrier provides galvanic isolation of up to 6000 VPEAK. When used in combination with a digital filter, the ISOSD61L device can be used to achieve 16-bit analog-to-digital (A/D) conversion with no missing codes.

主要特性

Low voltage differential signaling
6 kV galvanic isolation
30 kV/µs high common-mode transient immunity
16-bit resolution, no missing codes
±320 mV full scale differential input signal range
Up to 25 MHz external clock input

High SNR (86 dB) and bandwidth (49 kHz)
–40°C to +125°C extended industrial temperature range
Coaxial and header pins available for flexible access to the inputs and outputs
LVDS digital I/O (ISOSD61L) with on-board termination resistors
Additional pads for the connection of a shunt current sensor

 
 
Search Datasheet?

Supported by EEWorld Datasheet

Forum More
Update:2025-07-02 22:03:48
  • I2C slave address problem
  • Several methods to solve EMI consistency,,,
  • What should the AD part circuit of the MCU AD detection look like?
  • How to configure the remote frame of the CAN module
  • ADuM4151, SPI isolation design
  • DS18B20 reading and writing problems.

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
community

Robot
development
community

About Us Customer Service Contact Information Datasheet Sitemap LatestNews


Room 1530, 15th Floor, Building B, No.18 Zhongguancun Street, Haidian District, Beijing, Postal Code: 100190 China Telephone: 008610 8235 0740

Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号