2019 Question C: Line Load and Fault Detection Device +828006A

1. Topic analysis

1. Measurement of resistance, capacitance and inductance component parameters

       The DDS signal comes from the high-speed AD-DA circuit board made in the laboratory. DDS is used to apply a sinusoidal excitation signal to it. The voltage signal waveform on both sides of the standard resistor is transmitted through the high-speed ADC to the microcontroller STM32F407 for communication using SPI. The microcontroller obtains the actual sum through the fft algorithm. The imaginary part, since the real and imaginary parts of resistance, capacitance, and inductance are different, can be used to determine what component it is, and then calculate its value based on the real and imaginary parts.

2. Judgment of load structure

First, DDS generates a sine wave of 0-100khz in steps of 10khz, and uses a high-speed ADC to synchronously sample two points of the standard resistor. The MCU uses the FFT algorithm to calculate the voltage of the two points of the standard resistor, calculates the gain of the output compared to the input, and obtains the amplitude-frequency characteristics. The load structure is finally determined by analyzing the amplitude-frequency characteristics .

There are 14 types of structure including mixed connection. Our group can only test 10 types. The remaining 4 types are too special and difficult to distinguish.

3. Short circuit and open circuit judgment

      The wire required by the question is a network cable, and its resistance is linearly related to its length. Therefore, a current source can be used to express the length of the wire as a voltage difference. However, because its resistance value is very small, a current source with a small current cannot meet the requirement, and the current source itself Affected by temperature drift, measuring the voltage at both ends of the wire alone will be very unstable. Therefore, we added a standard coil, compared its voltage with the voltage at both ends of the wire to be measured, and then fitted the short-circuit distance and voltage value. function, the corresponding short-circuit point position can be obtained.

      The circuit break judgment is relatively simple, just directly judge whether the voltage difference across AB is close to 0V.

2. Hardware design ideas

Overall flow chart:

1. Current source

We adopted the 500mA Electronic Load solution in the routine Voltage_to_Current in TINA-TI to meet the large current of 500mA required by the problem, so that the wire resistance of a few ohms can be converted into a voltage of hundreds of milliamps, which is convenient for ADC measurement.

2. Relays and analog switches

      The signal frequency is not high, so the relay does not need to be a high-speed relay, just use an ordinary relay. We use the HRAH-S six-pin relay, which has a simple structure and is easy to control.

The analog switch uses CD4053, the voltage difference at both ends of the standard coil is connected to ax-bx, the voltage difference at both ends of the wire to be tested is connected to ay-by, and the common output is ao-bo.

3. Amplifier

      Since the voltage difference generated by the current source through the internal resistance of the network cable is small, and the output of the front-end analog switch is a differential signal, we choose the INA128 low-power precision instrumentation amplifier to amplify the voltage difference by 5 times, as close as possible to the minimum range of the ADS8691.

      The gain resistor selection is shown in the following table:

Since noise needs to be added to the performance part of the problem, a 104 capacitor can be pulled down after R8R9 to form a passive low-pass filter.

4. DC ADC

    Since the problem requires adding noise, we chose the ADS8691 with its own internal low-pass filter. This device is powered by a 5V analog single power supply, but supports ±12.288V, ±6.144V, ±10.24V, ±5.12V and ± 2.56V actual bipolar input range and 0V to 12.288V, 0V to 10.24V, 0V to
6.144V and 0V to 5.12V unipolar input ranges. The gain and offset error of each input range can be adjusted within a specific value range to ensure high DC accuracy.

    Through the amplifier in the front stage, the DC voltage is amplified to a level close to the most accurate minimum range of 0V to 5.12V.

5. High speed ADDA

It is used to provide the sinusoidal signals required for measuring components and structures, and to collect the signals at both ends of the standard resistor. Considering that two channels of signals need to be collected, we choose dual-channel ADDA chips, and the main control is controlled by FPGA EP4CE6E22C8.

The ADC chip uses ADS5553 dual-channel, 14-bit, 65MSPS, and the front-end input signal is through a fully differential amplifier.

Once the signal is captured at the input, the input samples are sequentially converted through a series of small resolutions and the outputs are combined into a digital correction logic module. Both the rising and falling edges of the clock are used to propagate samples through the pipeline every half clock cycle. This process results in a data delay of 16.5 clock cycles, after which the output data is provided as 14-bit parallel words encoded in binary 2's complement format.

Timing diagram:

The pre-stage differential amplifier can be selected according to the input signal frequency corresponding to the requirements:

Each of the two ADCs provides data of 14 in two's complement format (D13 to D0, D13 is the MSB and D0 is the LSB), the data ready signal (CLKOUT) and the over range indicator (OVR) are equal to 1 when When the output reaches the full-scale limit. Additionally, output enable controls (pins 48 and 52) are provided to tri-state the outputs.

The reference circuit comes from the ADS5553 datasheet.

Chip manual Dual 14 Bit, 65 MSPS ADC datasheet (ti.com.cn)

The DAC chip uses DAC5672, 14-Bit 275 MSPS

Has two operating modes selected by MODE pin.

For circuit design, please refer to the datasheet of DAC5672:

Chip manual: Dual 14 Bit 275 MSPS DAC datasheet (Rev. D) (ti.com.cn)

Issues you need to pay attention to when designing circuits and drivers:

1. It is necessary to design a power supply with stable power supply. Because of the large power, the FPGA of our board becomes a little hot after being used for a long time.

2. ADC input impedance matching and DAC output impedance matching.

3. When the sampling frequency of the ADC is low, the output data is always the default value. Because the input port of the ADC is connected to a capacitor, the signal can only pass when the frequency is relatively high.

4. The output voltage of a fully differential operational amplifier should theoretically be symmetrical to CMA or CMB, but the actual maximum output voltage is close to CMA and CMB.

Let’s do a simulation first to see the situation.

The relationship between the output voltage and input voltage of a fully differential op amp

You can see the voltage measured by the ADC

High-level input voltage 2.4V
Low-level input voltage 0.8V

Reference voltage 

REFSEL Reference voltage selection port
Reference select. 1 → EXT. REF; 0 → INT. When REF
is pulled low, the default output is positive voltage.

internal reference voltage

Reference bottom voltage, VREFM 1.01V
Reference top voltage, VREFP 2.16V

Use singTap to sample the waveform of the input signal. Initially, the frequency of the input signal is relatively low.

The sampling frequency is relatively high, and the data stored in the 2K memory is incomplete, so the actual waveform cannot be seen.

3. Software design ideas

The main function repeatedly judges the situation with a cycle of 1s, and short circuit has the highest priority.

Measure the distance function and determine the voltage range at the same time to determine whether it is a short circuit. If not, return 0 to determine other states.

To determine the structure function, perform fft on the waveform measured by the ADC and then determine the structure type.

float z_standard[2],z_standard_module;//real part + imaginary part of standard impedance

float RX,CX;//Resistance value and parasitic parallel capacitance of the resistor

FPGA DAC driver module refreshes address, reads data from ROM, and outputs data

Set the output frequency of DDS

4. Physical functional testing

Measuring short circuit point: 35cm, error within 1cm

The frequency sweep signal is provided by FPGA:

See the video for the detailed test, which meets the basic requirements and functional parts of the question and complies with the description of the question. No manual intervention is required. The device can automatically detect load changes, fault alarms and short-circuit fault point location in real time. The position of the short circuit fault point is shown to be stable.

Test video:

Basic part: Line load and fault detection device test video

Playing part: Line load and fault detection device playing part