#the4thLichuangcompetition# Portable high-speed arbitrary waveform generator

Brief introduction to the work: This project designed a very small, portable and low-cost arbitrary waveform generator with a volume of only 80x44x5mm, slightly smaller than a credit card. It can be easily carried in your pocket and supports lithium battery power supply and can be used immediately after taking it out. In terms of performance, the DAC waveform output sampling rate can reach 100MSPS, it can output sine waves below 25MHz and arbitrary waveforms below 5MHz, and the waveform amplitude and offset are adjustable. 1. Details of the work; This design uses the architecture of MCU+CPLD+SRAM+DAC to realize the high-speed DDS structure, uses MCU to perform waveform operations and generate waveform lookup tables, and uses CPLD with high-speed SRAM to achieve high-speed output of the lookup table. After receiving the data from the MCU, the CPLD writes the data to the SRAM in a FIFO manner, and then cyclically outputs the lookup table data to the DAC at a certain rate to achieve high-speed and arbitrary waveform output.

Technical parameters: Waveform sampling rate: 100MSPS Number of output channels: 1 Maximum frequency: 25MHz Basic waveforms: sine wave, square wave, triangle wave, sawtooth wave, SINC pulse extended waveform: customizable lookup table length: 512KB Analog front-end 3dB bandwidth: 25MHz Output waveform peak value: less than 5MHz: 40mVpp~5Vpp less than 25MHz: 40mVpp~2Vpp Output waveform offset range: -3.3V~+3.3V Output impedance: 50ohm Output shutdown leakage current: 1uA Output shutdown maximum peak withstand voltage: 300V Power supply: 5V-USB_Mirco input or built-in lithium battery

The programming software and EDA tools used in this design: LCEDA matlab Filter Solutions Keil MDK quartus Multisim ModelSim JFlash Visual Studio

2. Describe the challenges faced by the work and the problems it solves; At present, the common waveform generators (signal sources) in electronic laboratories are all desktop, which are large in size, heavy in weight, high in power consumption, and difficult to move and portable. And its price is unaffordable for groups such as students, makers, and electronics enthusiasts. As one of the four major components of the laboratory (oscilloscope, signal source, regulated power supply, and multimeter), without the signal source, it is impossible to provide incentives for the debugging of many circuits. It has become a blind man in circuit debugging, resulting in the failure to complete many experiments. Therefore, this project is here to solve this problem. The purpose is to design an arbitrary waveform generator that is cost-effective, has good performance but low cost, is portable (can be powered by mobile devices), and can be used in environments other than laboratories. Although there is some gap in function and performance compared to commercial finished signal sources, it has achieved good performance at an acceptable level at the existing cost. It can be said that it is easy to debug audio-level equipment. For MHz-level Low speed circuits can also do the job. Pain points targeted by this design: Many foreign open source waveform generator solutions use MCU to directly interface with DAC. Such waveform generators have a DAC sampling rate of several hundred KSPS at most, and can only generate waveforms of tens of KHz, sometimes even with audio. Level application debugging is a bit difficult; compared with the MCU direct push solution, this design breaks through the low bandwidth problem of the MCU and increases the waveform output sampling rate by 2-3 orders of magnitude to 100MSPS, which greatly improves the waveform output speed; relatively Due to the use of an integrated DDS (such as AD9851, AD9833), these integrated DDS can generally only output simple sine waves and square waves. They are really powerless for situations where complex waveforms are required. However, this design can achieve the output of arbitrary waveforms, even for users Programming waveform output; Compared with designs implemented using professional FPGAs, the price of an FPGA often ranges from hundreds to thousands. This design chose a compromise CPLD solution, which costs only a few yuan. Although in some high-speed The performance will be limited in complex tasks, but it will bring about reduction in size, power consumption, and most importantly, cost reduction. The BOM cost can be reduced to double digits, which reduces the cost for students, makers and other groups. The threshold for owning a waveform generator.

3. Describe the key points involved in the hardware and software parts of the work; The hardware design part is divided into four parts: low-speed human-computer interaction part, high-speed digital part, high-performance analog front-end part and power supply part. The software design part is divided into two parts: STM32 programming and CPLD programming (using the hardware description language Verilog)

Hardware part 1. For the low-speed human-computer interaction part, it is mainly composed of MCU and peripheral screen buttons and other human-computer interaction components. The connection between the screen and the MCU and the connection between the CPLD and the MCU both use an 8-bit parallel port. Two three-way button ports support large dial buttons and rotary encoders. They are designed to be connected to the encoder interfaces of timer 2 and timer 3 respectively. One important point in this part is that because the IO of the microcontroller is not enough, AD buttons are used. This design can use one IO to read 10 buttons. The circuit diagram is as follows. The AD button is designed to press the voltage at each point to support more than 10 buttons. The program reads the ADC every 1ms, and then performs debounce and button service. It can distinguish between short press and long press, but it does not support multiple keys at the same time. Press. 2. For the high-speed digital part, it mainly consists of three devices: CPLD chip-EPM240, high-speed SRAM chip-IS61LV25616AL, and clock generation chip-ICS511. The first is clock generation. Only the support of a high-precision, low-jitter high-speed clock can ensure the accuracy of waveform generation; the crystal oscillator used is a 25MHz crystal oscillator provided by Jiali Bandage, the manufacturer is YXC, and the accuracy is 10ppm. The PLL chip used is ICS511, which can provide 2-8 times programmable multiplier output, up to 200MHz. Its jitter performance is excellent, the absolute clock cycle jitter is +-70ps, and the single-cycle clock jitter is 20ps. In this paper The design provides a stable clock of 100MHz for digital high-speed systems. The second is the high-speed SRAM chip. As the cache of the lookup table, ISSI's IS61LV25616AL-10 is selected. This is a high-speed asynchronous static RAM. Compared with SDRAM, the operation is much simpler. No refresh operation is required, which saves CPLD. The internal logical resources are already compact. The access interface of this SRAM is 256Kx16 bits, and the interface access speed reaches 10ns, which means it can reach an access bandwidth of 200msps, which is enough to support the DAC data throughput requirements of this design. The lookup table length is 512K, which also meets the majority of waveform generation. application requirements. The CPLD chip is the core driver of DDS. It reads the lookup table data from the SRAM cycle by cycle from the obtained clock and outputs it to the DAC, providing a stable and accurate data update rate at equal intervals. The DAC chip is ADI's AD9708, which is an 8-bit 100Msps high-speed DAC. In order to facilitate compatibility between series, the chip package supports 14-bit data. In the circuit design, all 14-bit data channels are linked as a compatible design, which can be upgraded to higher precision in the future. DAC. 3. The high-performance analog front-end part can be said to be the soul of this project. Without a good analog front-end, it is impossible to output clean waveforms. The analog front-end in this design mainly has four functions: DAC output filtering, signal gain control, signal offset control and output drive and protection. According to the principle of DAC, the DAC output needs to be connected to a reconstruction filter to eliminate high-order harmonics. Wave. Because the DAC output is a current-type output, a ninth-order passive Butterworth filter is designed here to implement the reconstruction filter. Use professional filter design software to design the filter as shown below (because inductors and capacitors need to be purchased with a certain accuracy, so the curve is offset due to approximation). The simulation results are 3dB attenuation frequency point and stopband frequency point. The final circuit design uses differential Current structure corresponds to physical design

The signal gain control part uses ADI's AD603 chip, which is a voltage-controlled variable gain operational amplifier. In this design, its gain range of -11dB to +31dB is selected. At this time, the chip has a bandwidth of 90MHz, which is sufficient to meet the design needs. Using the DAC output of stm32 and converting it to +-1V can achieve digital controllability of the signal peak-to-peak value from 40mV to 5V. Signal offset control uses ADI's AD8042 high-speed operational amplifier. One of the AD8042 is a rail-to-rail high-speed dual operational amplifier with a 3dB bandwidth of 160MHz and a slew rate of 200V/us, which can meet the needs of high-speed signal output. The circuit that implements offset control and output drive and protection is as shown below. The final drive output drive is in one direction, and you can choose whether to design amplification or not. AD8042 can increase the output current up to 50mA, which is enough to drive common loads. The output switch is controlled by AQY210 optocoupler and has dual diode overload protection. The voltage used for gain control and offset control comes from the built-in DAC of stm32. Its output is 0-3.3V, while gain control requires +-1V and offset control requires +-3.3V, so an operator is required. to complete the conversion. But there is a problem involved here. The system power supply is +-3.3V. There are very few operational amplifiers that require input and output rails with a voltage resistance of more than 7V. Indeed, 5.5V voltage-resistant operational amplifiers are made with cmos technology and can easily realize input and output. Rail to rail, but the CMOS process cannot withstand too high a voltage. High-voltage op amps are mostly triode processes. Most of them can only reach the ground rail, and very few can reach the power rail. After searching for a long time, I finally found ON Semiconductor's MC33202. This op amp can withstand voltage up to 12V, which solves the problem. The control voltage mapping circuit is as follows

There are two options for the power supply part. You can choose the analog domain +-3.3V, which has lower power consumption and is suitable for battery use. The analog domain +-3.3V is composed of LDO + negative voltage charge pump. You can choose the analog domain +-5V, which can double the power consumption. Suitable for high-performance applications. It has a wide output voltage range. The analog domain +-5V is composed of BOOST DCDC. Different functions are realized through optional welding. The analog ground and digital ground are carefully designed for ground processing, and a single ground is designed closest to the DAC. Connect the analog and digital ground points and set up a complete ground plane for the key filter amplification loop and fully ground it.

The software part of the microcontroller is programmed using modular programming. Each waveform has an independent module, which makes it very convenient to add or delete waveforms and adjust the order of waveforms. It is also very convenient to customize different parameter operations and functions for each waveform, etc., which is quite flexible.

Because the competition requires that there must be a logo on the PCB board and a close-up of the logo in pictures and videos, and the location of this PCB is very compact, the competition logo can only be placed under the TF card holder package, so the TF card holder was not soldered during the competition. In the future, various extended waveforms, custom waveforms and other waveforms will be able to be stored and imported through TF cards or directly distributed via USB. This is the future upgrade goal.

The SIN value lookup table uses MATLAB to generate the MATLAB code as follows: See the attachment for the code file.

The SINC function generates a lookup table and also uses MATLAB to generate the MATLAB code as follows: See the attachment for the code file.

The CPLD program involves writing in Verilog hardware description language and developed using ALtera's official EDA, QuartusII 13.0.1. The picture below is a screenshot of the top-level code. Since most friends have no experience in developing programmable devices, here is a brief introduction to how to synthesize and burn them. First prepare to download QuartusII and purchase USB Blaster. Create a project, select devices, add files and other processes. You can find tutorials on the Internet. Click the purple circle to edit pin associations. Click the red circle arrow to start integrated wiring. Click the blue circle to download. Pin definition download process. Plug in the USB Blaster. Use the JTAG port to connect the JATG of the target board Blaster. Pin definition , click on the red circle in the download interface, select the file to be downloaded, check the download selection, click start and wait for the download to complete. Please see the attachment for the .pof file to be downloaded.

Regarding the host computer being developed, the development environment Visual Studio uses the C# language. The host computer code/project screenshots are currently at the beginning of the semi-finished product, but there is a shelf that has not been finalized, and many displayed parameters have not been finalized. The last semi-finished product picture is only for For reference, the data inside is not the final result, because the deadline for the competition is about to be completed, and if you can’t finish it, you can only work on it slowly later.

4. Upload the picture of the work; the appearance of the PCB proofing returned. Thanks to the SMT proofing service provided by Lichuang, which saves a lot of welding work. The back of the blank board is welded, the front is welded, the back is welded , the screen is welded, and the size in the hand is compared with the Beijing Transportation Card ( credit card) size

Output performance diagram: Maximum output of 25MHz sine wave, 200K sine wave, sawtooth wave output, SINC output, square wave output, triangular wave output, staircase wave output, minimum amplitude output

5. Material list of the work;   BOM table is shown in Lichuang EDA, see the attachment. 6. Open source documents; PCB files, please see Lichuang EDA. Open source programs and executable files are in the attachment. 7. Demonstration video: see the attachment.