Shock! I actually drew the chip layout in Lichuang EDA!

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This project uses Lichuang EDA to design a basic power MOS layout, in order to facilitate the learning of friends who understand the structure and principles of the device.

1. Here is a brief introduction to the difference between power MOS and ordinary MOS.

The basic requirement for traditional MOSFET operation is to apply a voltage on the gate electrode to form a conductive channel on the semiconductor surface under the gate insulating layer. This kind of MOS source and drain are crossed and can only be realized with thin metal electrodes, resulting in this The horizontal design structure cannot withstand high withstand voltage or large current.

Traditional MOS structure diagram

In the vertical structure, the two electrodes that transmit large currents can be placed on the front and back sides of the silicon wafer, thereby avoiding the use of thin metal cross-current transmission structures. In addition, the potential divisions of the vertical structure are more suitable for withstanding high withstand voltages.

VD-MOSFET (Vertical-Diffused) vertical diffusion field effect transistor grows an N-type epitaxial layer on a heavily doped N+ substrate. The channel is formed by the difference in the depth of the two lateral diffusion junctions of the P-type base region and the N+ source region. , these two areas are injected with their respective doping impurities through the gate self-alignment process during the ion implantation process.

When no gate voltage is applied and the drain is positively biased, the VDMOSFET structure can withstand high voltages. At this time, the J1 junction formed by the P-type base region and the N-drift region is reverse biased, and the voltage is mainly borne by the thick lightly doped N-drift region. When a positive voltage is applied to the gate electrode, a drain current is generated in the MOS structure. An inversion layer is formed on the surface of the P-type base area under the gate electrode. When the drain is forward biased and the gate potential is positive, J2 to J1 form an inversion layer channel to provide an electron transmission path from source to drain.

References: [1] B.Jayant Baliga. Fundamentals of power semiconductor devices [ M ]. Electronic Industry Press, 2013: 153-154

                  [2] Robert F. Pierret. Basics of Semiconductor Devices[M]. Electronic Industry Press, 2004:441

All in all, vertical MOSFETs are symmetrically folded from traditional MOS. Generally, the MOS tubes you use adopt this structure.

Schematic diagram of VDMOSFET structure cell

The picture below shows the layout of VDMOS, which is mainly composed of the internal Cell unit and the surrounding terminal structure. The function of the terminal junction is to ensure that the edge part of the device can meet the voltage withstand requirements under high voltage conditions.

Power VDMOS device layout

2. Next, we will introduce the production process of power VDMOS devices and the corresponding layouts used in this project.

1. Substrate preparation

In order to meet the requirements of high withstand voltage (200~1000V), the substrate material needs to be selected with high resistivity, and the lattice structure must be complete and defect-free, and its crystal orientation and carrier lifetime must have high uniformity and authenticity. . Therefore, the silicon single crystal adopts the <100> crystal orientation, and arsenic is selected as the substrate material. Its resistivity needs to be calculated based on the design withstand voltage, so that the substrate resistance is extremely small. Then a layer of N-epitaxial layer is grown on the substrate, and subsequent processes are performed on the epitaxial layer.

2. Terminal doping

Use the mask1 terminal structure photoresist, and use the photoresist as a masking layer to perform boron ion implantation (the red color of the terminal structure layout is the injection area) to form the junction depth of the terminal structure. This ion implantation does not enter the cell area, and under high-temperature annealing Impurity ions are activated, ultimately forming a deep P-junction in the terminal region.

3. Field oxidation growth

Grow a 10000A field oxide layer, and use the mask2 source area photoresist to etch the active area to form the source area. The purpose is to isolate the cell area from the terminal area. The subsequent process is mainly based on the cell area process. The cell area also needs to inject phosphorus ions and activate impurity ions under high-temperature annealing to finally form the JFET area (the green color of the source area layout is the part of the JFET area to be etched)

4.Gate electrode growth

Grow a 600A gate oxide layer and 5000A polysilicon, and use mask3 silicon gate photolithography to etch the polysilicon to make the gate electrode (the blue color of the silicon gate pattern is the remaining part of the polysilicon after etching)

5. Boron ion implantation

Form the Pbody area. Polysilicon and field oxidation can block the entry of ions, which is called self-alignment. It acts as a layer of photolithography, which can save costs. After high-temperature push-bonding, the Pbody area is formed.

6. Source region doping

Use mask4 source area photolithography to prepare the photoresist masking layer, and perform arsenic ion implantation to form the N+ source area (the yellow color of the source area layout is the remaining part of the photoresist after development)

7. Preparation of dielectric layer

At this point, it can be seen that the basic structure of the MOS has been formed, and the subsequent process is to make the contact electrode. Deposit a layer of 10000A BPSG phosphosilicate glass dielectric layer to isolate the gate and source.

8. Contact hole etching

Because the device is composed of multiple unit cells connected in parallel, it is necessary to use metal to connect them together and lead out the electrodes G and S. In order to see the connection more intuitively, you can use the sleeve and diagram to identify the connection between the gate and the source (the purple part of the metal layout is the corroded part)

At the same time, a layer of metal must be deposited on the back to form the drain electrode.

10. Pressure point etching

After the metal preparation is completed, the MOS will have electrical properties. At this time, the final pressure point etching needs to be performed. In order to protect the chip from failure due to moisture absorption, external particles, etc. that affect the electrical performance, a layer of protective glue needs to be coated on the surface for protection. Use mask7 pressure point photolithography to only open the required orange area for subsequent packaging, and the rest is For photoresist protection part

11.Testing

At this point, all processes have been completed. The finished chip needs to pass the test of various electrical parameters before it can be sent to packaging.

MOS tube after packaging and wiring

3. Actual process steps (silvaco simulation)

This part mainly introduces the process steps of the CELL area.

1. First prepare the silicon wafer for epitaxy. If it is N-type MOS, the substrate is N-type, and subsequent processes are processed on the epitaxial layer.

The withstand voltage of general devices is largely determined by the thickness and resistivity of the epitaxial layer (the thicker the epitaxial layer, the greater the resistivity, the greater the BVDSS withstand voltage, and the greater the relative RDSON)

Epitaxial silicon wafer:

2. Gate oxide layer and gate electrode preparation

First, a very thin oxide layer is grown on the epitaxial layer as the insulating layer between G and S. Generally, the thickness is only a few hundred to tens of nm. Then a polycrystalline layer is deposited on the gate oxide layer as the subsequent gate electrode.

Gate oxide and gate electrode:

3. Gate etching

Apply a layer of photoresist evenly, and use the second part of the mask3 photoresist to expose it to form a gate pattern to prepare for the next step of etching.

Photoresist:

After exposure and development:

After etching: Etch away all the unprotected areas of the photoresist, leaving the required parts

4. Boron ion implantation

Boron ions are implanted to define the Pbody region. Polysilicon and field oxidation can block the entry of ions, which is called self-alignment. It acts as a layer of photolithography. After high-temperature pushing, the Pbody region is formed.

Before ion implantation: uniform distribution of doping

After injection: forming P-type body region

After high temperature annealing: push knot

5. Source region ion implantation

Use mask4 source area photolithography to prepare the photoresist masking layer. After photolithography and development, arsenic ion implantation is performed to form the N+ source area.

After arsenic ion implantation: the black line in the picture is a PN junction

Comparing the structure diagram, now the basic structure of a VDMOS has been formed, and metal interconnection can be carried out later.

6. Dielectric layer processing and contact hole etching

Planarize and densify the oxide layer covering the gate to ensure insulation and reliability, and prepare for subsequent hole etching and metal contact.

7. Metal deposition and etching

Lead out the electrodes G and S, and the back side is the D pole.

The actual process steps will be much more complicated than those described above, and the structure will be more complicated than the above picture. Here is just a brief introduction. Interested students can check the information by themselves.

The simplest MOS tube generally requires hundreds of processes, and the more complex CMOS process can reach thousands of processes. Each process is essential.

Is not it simple? You can do it after watching it (dog head)

4. The following content needs to be supplemented