XC9500/XC9500XL series CPLD is an early CPLD product of Xilinx. IO; those with XL suffix support up to 3.3V power supply, but allow 5V CMOS signals or 5V TTL signals to be input normally without damaging the device. The output voltages are all from GND to VCCIO.
The internal structure of this model of CPLD is relatively simple and reliable. Although it cannot be used as a mainstream commercial or learning device, it is widely used in nostalgia projects and other aspects.
Its internal structure is as follows:

Taking XC9572/9572XL as an example, it has many Various packages, such as PLCC84, PLCC44, QFN44, etc. The 44-pin version has three VCCs, three GNDs, and a 4-wire JTAG serial port download interface. The remaining 34 pins are all user-available IO ports, and all support input and output. Six of the interfaces can be directly connected to the internal clock, enable, and reset buses to increase conversion speed.
The following is the download process:
1. Use xilinx ISE/Vivado and other software to write v files and ucf files, and compile and generate jed netlist files
. 2. Use IMPACT software to download and open IMPACT software.
Prepare the following hardware: Scan, then right-click on the blank space on the right, and click Initialize Chain to initialize the download link.
You can identify the model as shown below
. 3. Double-click the symbol of the chip, and a dialog box will pop up. At this time, select the jed file just generated
4. This When right-clicking on the chip, the programming button will not pop up. We also need to reset the CABLE connection. Click as shown below:
Then right-click on the chip icon and you will see the Programme button.
5. Click the download button and wait a few seconds. After the download is completed in
more than ten seconds, the download process is completed. At this time, you can cut off the power, disconnect the cable, and then power on the development board to see that the previously downloaded logic is running normally.