【FC Custom Mapper】595 Lowset Cassette

The maximum supported capacity of PRG ROM and CHR ROM is 512kB.
Bank mapping is similar to Mapper 78.
 
Overview:
PRG ROM Bank Size: 16kB
CHR ROM Bank Size: 8kB
PRG RAM: Not Present
Name Table Mirroring: Managed
Bus Conflicts: Present (see here)
 
Bank Mapping:
CPU $8000-$BFFF: Switchable PRG ROM Bank, 16kB Total
CPU $C000-$FFFF: 16 ​​kB PRG ROM Bank, Fixed in Last Bank
PPU $0000-$1FFF: Switchable CHR ROM Bank, 8kB Total
 
Bank Select Data Input ($8000-$FFFF):
76543210 Bits
||||||||
|||+++++- Select 16kB PRG ROM Bank for CPU $8000-$BFFF
||+------ CHR Bank Register SER Data Bits
|+------- CHR Bank Register RCLK Commit Bits
+-------- CHR Bank Register SRCLK Save Bits
 
CHR Bank Select:
76543210 Bits
|||||||||
||++++++- Select 8kB CHR ROM Bank for PPU $0000-$1FFF
|+------- Name table mirror state selection [0: State A (Screen A, horizontal); 1: State B (Screen B, vertical)]
+-------- Name table mirror mode selection (0: Single screen mirroring; 1: Horizontal and vertical)
 
Please also note:
If you need to display the game screen and the status bar separately, then when the No. 0 sprite collides, a certain number of CPU cycles are required to change the CHR ROM register data, and then RCLK can be sent to submit, causing the screen to display different content in a specific part, affecting the appearance. Therefore, if this design is required, the CHR ROM register data should be changed first, but RCLK should not be sent to prepare. When the No. 0 sprite collides, RCLK will be sent again to complete the switch. In addition, this requirement is optional. If the game screen and the status bar are to use different CHRs, this requirement must be followed.