CN0162

Analog audio input, Class D output via ADAU1701 SigmaDSP codec, low-power SSM2306 Class D amplifier and ADP3336 LDO regulator

Schematic PCB

12-Bit, 2GSPS Data Acquisition Reference Design

By interleaving Renesas' low power, high sample rate ADCs, it is possible to achieve a combination of ultra-high sample rate and very high dynamic range that is not available in today’s stand-alone ADCs. This reference design demonstrates the performance attainable by combining Renesas' ADC technology and SP Devices' interleaving algorithms. In this design, four ISLA112P50 12-bit, 500MSPS analog-to-digital converters are interleaved to sample at a rate of 2.0GSPS. At this sampling rate, the reference design provides over 6dB more SNR and 13dB better SFDR than the best alternative stand-alone ADC.