syzygy-dual-atto320: SYZYGY to dual Atto320 LWIR sensor

SYZYGY is an FPGA extension standard for medium to high speed interfaces. This design is a breakout board for connecting dual Atto320 LWIR sensors. Designed to mate with existing sensor breakout boards that provide FFC connectivity.

Schematic PCB

syzygy-breakout: Breakout board for standard SYZYGY connectors

SYZYGY is an FPGA extension standard for medium to high speed interfaces. This design breaks out all 32 I/O pins into taps with 0.1" headers. A small prototyping area is also provided.​

Schematic PCB

rpi-hq-camera: Connector for Raspberry Pi HQ camera

This design is a connector for the Raspberry Pi HQ camera.

Schematic PCB

icebreaker++-ram: icebreaker FPGA board, upgraded with ECP5 (+extra RAM)

​It is a very beautiful and convenient little board. But it has a small flaw, the ice40 FPGA it uses is very simple, and it's generally fun to see people doing exciting projects with 5k LUTs. Sometimes it's convenient to have some extra space available when experimenting.

Schematic PCB

icebreaker++: icebreaker FPGA board, upgraded ECP5

icebreaker++ is a very nice and convenient little board. But it has a small flaw, the ice40 FPGA it uses is very simple, and it's generally fun to see people doing exciting projects with 5k LUTs. Sometimes it's convenient to have some extra space available when experimenting.

Schematic PCB

gpdi-serdes: GPDI using serdes

SYZYGY is an FPGA extension standard for medium to high speed interfaces. This design splits the video output to a regular digital display and also supports input from the digital display. It connects to the SERDES via a SYZYGY-TXR connector. Would love to be able to test the 5Gbps output of high resolution GPDI.

Schematic PCB

GPDI: SYZYGY interface board with 2 digital video ports

SYZYGY is an FPGA extension standard for medium to high speed interfaces. This project is a splitter that outputs video to a regular digital display and also supports input from a digital display.

Schematic PCB

ecpbreaker: Based on icebreaker FPGA board, upgraded ECP5

The icebreaker project is a very nice and handy little board. But it has a small flaw, the ice40 FPGA it uses is very simple, and it's generally fun to see people doing exciting projects with 5k LUTs. Sometimes it's convenient to have some extra space available when experimenting.

Schematic PCB

ZYNQ version of high-performance open source oscilloscope: 1Gsps sampling rate, 100MHz bandwidth, capture rate 22000 wfm/s, Raspberry Pi for waveform rendering

The biggest feature of this open source oscilloscope is its strong waveform rendering (afterglow/fluorescence) effect. At the beginning, the author used Raspberry Pi Module 3, which can render 22,000 frames per second. In the later stage, NVIDIA Jetson is used, which can render 130,000 frames. frame. ZYNQ's FPGA is responsible for triggering and data acquisition, and A9 is responsible for transmitting data to the Raspberry Pi. Then the Raspberry Pi does the display processing. The ADC uses 1Gsps HMCAD1511.

Schematic PCB

ScopeFun: Open source oscilloscope

ScopeFun is an open source all-in-one instrumentation platform. It includes oscilloscopes, arbitrary waveform generators, spectrum analyzers, logic analyzers and digital pattern generators.

Schematic PCB

Gigabit Ethernet PHY and PC point-to-point communication procedures and corresponding tests

The physical layer data sending and receiving of a PC is very simple. As long as one condition is met, that is, the CRC check of the data packet is correct, the network card can send the data packet to the application software. Otherwise, the network card will directly discard the data packet, which cannot be caught by any software. to the data packet.

Schematic PCB

CPLD portable digital storage oscilloscope hardware platform design

CPLD portable digital storage oscilloscope hardware platform design

Schematic PCB

12-Bit, 2GSPS Data Acquisition Reference Design

By interleaving Renesas' low power, high sample rate ADCs, it is possible to achieve a combination of ultra-high sample rate and very high dynamic range that is not available in today’s stand-alone ADCs. This reference design demonstrates the performance attainable by combining Renesas' ADC technology and SP Devices' interleaving algorithms. In this design, four ISLA112P50 12-bit, 500MSPS analog-to-digital converters are interleaved to sample at a rate of 2.0GSPS. At this sampling rate, the reference design provides over 6dB more SNR and 13dB better SFDR than the best alternative stand-alone ADC.

KPower supply design for Kintex Ultrascale FPGA: ultra-quiet, 1.8V, 1A

This reference design provides a power-supply circuit with an input voltage of 3.3V, an output voltage of 1.8V, and an output current of 1A using the MAX8869 low-dropout linear regulator. The circuit was developed to power a MGTVCCAUX rail on a Xilinx® Kintex® Ultrascale™ FPGA. Included in this reference design are a schematic and a bill of materials.

Schematic PCB

Power supply design for Kintex Ultrascale FPGA: PMBus compatible, strictly regulated, 1.80V, 2A

This reference design provides a power-supply circuit with an input voltage of 10.8V to 13.2V, an output voltage of 1.80V, and an output current of 2A using the MAX15303 InTune™ Point-of-Load (PoL) Controller. The circuit was developed to power a VCC1V8 rail on a Xilinx® Kintex® Ultrascale™ FPGA. Included in this reference design are a schematic, applications information, and a bill of materials.

Schematic PCB