Where can I find the delay parameters of the FPGA in the calculation of the SDRAM clock phase shift?

jiabujia

Where can I find the delay parameters of the FPGA in the calculation of the SDRAM clock phase shift? [Copy link]

The calculation formula for SDRAM clock phase shift is given in Altera's official manual Embedded Peripheral IP User Guide. The document says that the FPGA delay parameters are in the compiled file, but I haven't found it after searching for a long time. I hope the experts can give me some advice.

reallmy

This is tco, which is a hardware parameter, and you can't change it!!! What you need to do now is that after your output signal is given to the lower-level chip, the lower-level chip must meet its own setup time and hold time. If it does not meet the requirements, you need to adjust the relative relationship between your output signal and the output clock. This is generally done with output delay for timing constraints. You can check this time in the chip planner, where there is something like an alarm clock. Click on the path to display the time! I can't remember the details, so study it yourself!

reallmy

I don't know what delay you are looking for. Generally, the delays inside FPGA, such as register to register, pin to pin, reg to pin, are in time quest and also in chip planner!

jiabujia

reallmy posted on 2017-1-20 16:30 I don't know what delay you are looking for. Generally, the delays inside FPGAs, such as register to register, pin to pin, reg to pin, etc., are in time quest, and...

Thank you for your advice. What I am looking for is the data output delay time (Clock-to-Output Delay) of FPGA. I only found the clock setup and hold time in timequest

jiabujia

reallmy posted on 2017-1-20 16:30 I don't know what delay you are looking for. Generally, the delays inside FPGAs, such as register to register, pin to pin, reg to pin, are in time quest, and...

are the parameters here

jiabujia

reallmy posted on 2017-2-9 15:10 This is tco, it is a hardware parameter, you can't change it!!! What you need to do now is to give your output signal to the lower-level chip, and the lower-level chip must...

Thank you for your advice

reallmy

Generally speaking, if you put the output to IOB and the output clock to ddio, the timing can basically be met! ! ! You should learn about it! It is very important!