Mitigating Overheating in Hyperscale and Ultra-Scale FPGA Applications

Precision and reliability are top priorities in industrial and consumer embedded applications, such as motor control and high-precision medical equipment. Any failure in these types of systems can be devastating and cost the company millions of dollars. The most common point of failure is the system's power supply, with overheating and unmonitored power rails being the most common cause of failure.

The traditional approach to avoiding these faults is to use remote point-of-load solutions, which can be bulky and consume significant board space. Furthermore, implementing power monitors on every system power rail increases system cost. Hot spots in power ICs are often located near the power FETs through which the current flows. A simpler and more cost-effective approach is to separate the power FETs from the main power IC, which results in better heat dissipation, and implement active monitoring using a power-good signal to monitor the power rails.

By using an integrated PMIC like the TPS650860, we can achieve the same level of reliability without the high cost of multiple ICs. The device's architecture allows us to avoid overheating while monitoring each power rail for system safety. The power-good signal implemented on each rail protects our system from undervoltage lockout and overvoltage triggering. Each rail can be programmed to monitor within very tight tolerances.

    The TPS650860 device is a single-chip power management IC designed for multi-core processors, FPGAs, and other systems-on-chip (SoCs). The TPS650860 offers a 5.6 V to 21 V input range, enabling a wide range of applications. The device is ideal for both NVDC and non-NVDC power architectures using 2S, 3S, or 4S Li-ion battery packs. For a 5V input supply, see the Applications section. The D-CAP2™ and DCS-controlled high-frequency voltage regulator utilizes small inductors and capacitors to achieve a small solution size. The D-CAP2 and DCS control topologies offer excellent transient response performance, making them ideal for processor cores and system memory rails with fast load switching. An I²C interface allows for simple control via an embedded controller (EC) or SoC. The PMIC is housed in an 8mm × 8mm single-row VQFN package with a thermal pad for excellent heat dissipation and easy board routing.

    ▲Features:
● Wide V-IN range from 5.6 V to 21 V
● Three variable output voltage synchronous buck controllers with DCAP2™ topology
■ Scalable output current using external FETs with selectable current limit
■ I²C DVS control from 0.41 V to 1.67 V in 10 mV steps, or from 1 V to 3.575 V in 25 mV steps
● Three variable output voltage synchronous buck converters with DCS control topology
■ Voltage input range of 4.5 V to 5.5 V
■ Up to 3 A output current
■ I²C DVS control from 0.41 V to 1.67 V in 10 mV steps, or from 0.425 V to 3.575 V in 25 mV steps
● Three LDO regulators with adjustable output voltage
■ LDOA1:l²C—Selectable output voltage from 1.35 V to 3.3 V at output current up to 200 mA
■ LDOA2 and LDO A3: l²C—Selectable output voltage range from 0.7 V to 1.5 V with up to 600 mA output current
● VTT LDO for DDR memory termination
● Three load switches with slew rate control
■ Up to 300 mA output current with less than 1.5% voltage drop across nominal input voltage
■ R-DSON < 96 mΩ at 18 V input voltage
● 5 V fixed output voltage LDO (LD05)
■ Gate driver supply for switching power supplies and LDOA1
■ Automatic switchover to external 5 V buck circuit for improved efficiency
● Built-in flexibility and configurability via factory OTP programming
■ Six GPI pins configurable as enable (CTL1 to CTL6) or sleep mode entry (CTL3 and CTL6) for any selected rail
■ Four GPO pins configurable as power supply for any selected rail
■ Open-drain interrupt output pin
● l²C interface supports:
■ Standard mode (100 kHz)
■ Fast mode (400 kHz)
■ Fast mode Plus (1 MHz)

Figure 1 shows the connection between the PMIC and the FPGA. The three buck controllers integrated into the device require external power FETs, which move any hotspots away from the PMIC. When the FPGA is running at full speed, moving the hotspots allows for better heat dissipation in harsh environments and ensures the reliability of the PMIC.

Figure 1: Connection diagram

In addition to offloading hotspots from the PMIC, the controller architecture allows us to scale the system size based on the power required by the FPGA; we can select the external FETs based on the current required for each power rail. We can design the system so that each rail can provide up to 10s of amplitude with an accuracy of +/- 3%. This, in turn, reduces system size and cost.

With all this flexibility, we can power multiple FPGAs with a simple OTP rotation and optimize the solution to mitigate thermal issues.