Using NE555 to delay the output of high level circuit

The power-on delay output high level circuit is shown in the figure below. When the power is turned on, since capacitor C has no time to charge, pins ② and ⑥ of the 555 time base circuit are at a high level, and pin ③ outputs a low level. As capacitor C charges, the potential of pins ② and ⑥ of the 555 time base circuit decreases. Until the potential of pin ② is lower than 1/3 Vcc, the circuit state flips, and pin ③ changes from a low level to a high level and remains so. The power-on delay time tw=1.1RC. The diode VD in the circuit is set to discharge capacitor C after the power is turned off. This circuit is generally used to control the delayed connection of high-voltage power supplies or control the delayed connection of other power supply circuits, so this circuit is also called a power-on high-voltage delay circuit.