Using 14-bit 125MSPS four-channel ADC circuit diagram

The circuit shown below is a simplified diagram of a 14-bit, 125 MSPS quad ADC system that uses back-end digital summation to increase the signal-to-noise ratio (SNR) from 74 dBFS for a single-channel ADC to 78.5 dBFS for a quad-channel ADC. This technology is particularly suitable for applications requiring high SNR (such as ultrasound and radar) and takes advantage of modern high-performance, low-power, quad-channel pipelined ADCs.

This circuit uses the basic principle that uncorrelated noise sources are summed on a root sum of squares (rss) basis, while signal voltages are summed on a linear basis.