Typical anti-interference timer circuit diagram

Typical anti-interference timer circuit

The figure shows a typical anti-jamming timer circuit diagram. The principle of this circuit: When SB is disconnected, pin 4 of 555 is connected to ground through resistor R6, and the 555 circuit is forced to reset. At this time, no matter how much interference is received by pin 2, the 555 circuit will not work. When button B is pressed, power is applied to pin 4 through diode VD1 to a high level, and the forced reset function of the time base circuit is released. At the same time, power is applied to the base of transistor VT1 through resistor R1, causing VT1 to conduct, and the capacitor C2 outputs a low level to pin 2 of the IC circuit after being connected to the collector of VT1. The IC flips and sets, pin 3 outputs a high level, the light-emitting diode lights up, relay K is energized, contact K-1 is closed, and the socket External power supply, while the high level of pin 3 outputs a high level to pin 4 through VD2 to make the circuit self-locking. When the transient state ends, the circuit returns to the steady state, pin 3 outputs low level, relay K loses power, contact K-1 is disconnected, and the circuit returns to the initial state.