High voltage current sensing using low voltage transistors

    Circuit used to monitor the negative rail, this circuit and all circuits using this topology are inspired by the current mirror topology and the concept that a changing current in Rsense and the voltage across Rsense changes the current in Re2 and therefore the voltage across Rc1 in a linear fashion.

    Figure 1 Circuit for monitoring the negative rail

    The circuit of Figure 1 owes its existence to Re1 and Re2. By making Ireffairly small and Re2 and Re1 very large and equal, the voltage at the emitter increases relative to the voltage across Rsense. This in turn reduces the change in Vce of the output device as the load varies between no load and full load.

    Therefore, by judiciously selecting Iref, Re1, Re2, Rc2, and Rc1, Q2 can be prevented from being driven into saturation without exceeding the transistor's maximum operating voltage. Remembering that hoe = I(collector)/VA (earth voltage), reducing variations in Ical reduces variations in β, thereby improving linearity. Rc is the sum of Rc1 and Rc2, so the ratio Rc1/Rc determines the offset at Vout− at no load. The voltage developed across Rsense at full load determines the change in current in Re2 and Rc1, and therefore the full-scale output at Vout−. Once the value of Iref is determined, calculating the required no-load voltage across Rc and Rd is straightforward. Using an emitter resistor significantly reduces the effect of Vce variations on Q2's β, and inspection of simulation data indicates that variations in β have a relatively small impact on the correlation between load current and output voltage. Given the results obtained, a configuration similar to the Wilson current mirror may not be necessary.

    Figures 2 and 3 show alternative solutions for a constant current source to generate Iref. If Vss is stable and ripple-free, the constant current generator can be omitted and the value of Rd can be chosen to provide Iref.

    Figure 2 shows another solution for generating Iref using a constant current source.

    Figure 3 sets the FET bias so that Iref does not cause Vce or Vds to exceed their maximum values during startup.

    Figure 4 inverts Vout−, removes the offset, scales the output to the desired range, and can filter the output to handle power supply ripple or load spikes. If using a microcontroller with an ADC, the circuit can be simplified to just invert Vout−.

    Figure 4 Inverting Vout− eliminates the offset, scales the output to the desired range, and can filter the output to handle supply ripple or load spikes.

    If V Re1 is at least 10 times greater than V Rsense at full load, Q2 will not saturate and

    V Rsense = (Iload + Iref) x Rsense 1

    V Re1 = 10(V Rsense(full load) ) 2

    Iref = I Re1, and when there is no load, that is, Iload = 0, therefore:

    Re1 = V Re1 / Iref = Re2 3

    Vccs is the voltage across the constant current source, I Re1 = Iref is very close, and Vbe can be 0.6 to 0.65V:

    Rd = (Vss – (Vccs + Vbe (Q1) + V Re1 )) / Iref 4

    Vce is the maximum voltage required across Q2 at no load. I Re2 is approximately equal to Iref, so:

    Rc = (Vss – Vce) / I (Re2) ≈ (Vss – Vce) / Iref 5

    The desired offset voltage at Vout− at no load determines the value of Rc1:

    Rc1 ≈ (Rc x Vout− (offset) )/ V Rc 6

    I Re2 at full load can be estimated because I (Rsense) = Iref / 10:

    I Re2 (full load) ≈ 1.1 x I ref 7

    At maximum load current, the full-scale value of Vout− is approximately:

    Vout− (full scale) – Vout− (offset) ≈ Rc1 x I Rsense(full load) 8

    LTspice was used to generate the following curves, which show the circuit's linearity, filtering effectiveness, and Vce and Vds during operation. The load current was increased from 0 amps to 1 amp, and the output voltage was superimposed on the load current. The results are similar to actual circuit performance. Filtering prevents tripping due to short-term spikes in load current. Isolation may not be required, but it should always be considered when designing high-voltage circuits.

    Figure 5 Vout without 25nF capacitor at C1 in Figure 4

    Figure 6 Vout with 25nF capacitor at C1 in Figure 4

    Figure 7 Voltage on active devices