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MT48V32M16LFFN-6A

Description
Synchronous DRAM, 32MX16, 5.4ns, CMOS, PBGA54, 10 X 12.50 MM, VFBGA-54
Categorystorage    storage   
File Size2MB,62 Pages
ManufacturerMicron Technology
Websitehttp://www.mdtic.com.tw/
Download Datasheet Parametric View All

MT48V32M16LFFN-6A Overview

Synchronous DRAM, 32MX16, 5.4ns, CMOS, PBGA54, 10 X 12.50 MM, VFBGA-54

MT48V32M16LFFN-6A Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerMicron Technology
Parts packaging codeBGA
package instruction10 X 12.50 MM, VFBGA-54
Contacts54
Reach Compliance Code_compli
ECCN codeEAR99
access modeFOUR BANK PAGE BURST
Maximum access time5.4 ns
Other featuresAUTO/SELF REFRESH
Maximum clock frequency (fCLK)166 MHz
I/O typeCOMMON
interleaved burst length1,2,4,8
JESD-30 codeR-PBGA-B54
JESD-609 codee0
length12.5 mm
memory density536870912 bi
Memory IC TypeSYNCHRONOUS DRAM
memory width16
Number of functions1
Number of ports1
Number of terminals54
word count33554432 words
character code32000000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize32MX16
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeVFBGA
Encapsulate equivalent codeBGA54,9X9,32
Package shapeRECTANGULAR
Package formGRID ARRAY, VERY THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)235
power supply1.8/2.5,2.5 V
Certification statusNot Qualified
refresh cycle8192
Maximum seat height1 mm
self refreshYES
Continuous burst length1,2,4,8,FP
Maximum supply voltage (Vsup)2.7 V
Minimum supply voltage (Vsup)2.3 V
Nominal supply voltage (Vsup)2.5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formBALL
Terminal pitch0.8 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperature30
width10 mm
ADVANCE
512Mb: x16
MOBILE SDRAM
MOBILE SDRAM
MT48V32M16LFFN, MT48V32M16LFBN,
MT48H32M16LFFN, MT48H32M16LFBN
8 Meg x 16 x 4 banks
For the latest data sheet revisions, please refer to the Micron
Web site:
www.micron.com/dramds
FEATURES
• Temperature Compensated Self Refresh (TCSR)
• Fully synchronous; all signals registered on
positive edge of system clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, includes CONCURRENT AUTO
PRECHARGE and Auto Refresh Modes
• Self Refresh Mode
• 64ms, 8,192-cycle refresh
• LVTTL-compatible inputs and outputs
• Low voltage power supply
• Deep Power Down
• Partial Array Self Refresh power-saving mode
BALL ASSIGNMENT (Top View)
54-Ball VFBGA
1
A
B
C
D
E
F
G
H
J
V
SS
DQ14
DQ12
DQ10
DQ8
UDQM
A12
A8
V
SS
2
DQ15
DQ13
DQ11
DQ9
NC
CK
A11
A7
A5
3
V
SS
Q
V
DD
Q
V
SS
Q
V
DD
Q
V
SS
CKE
A9
A6
A4
4
5
6
7
V
DD
Q
V
SS
Q
V
DD
Q
V
SS
Q
V
DD
CAS\
BA0
A0
A3
8
DQ0
DQ2
DQ4
DQ6
LDQM
RAS\
BA1
A1
A2
9
V
DD
DQ1
DQ3
DQ5
DQ7
WE\
CS\
A10
VDD
OPTIONS
• V
DD
/V
DD
Q
2.5V/2.5V–1.8V
1.8V/1.8V
• Configurations
32 Meg x 16 (8 Meg x 16 x 4 banks)
• Plastic Packages
54-pinTSOP (400 mil)
1
54-pinTSOP (400 mil) Lead-Free
1
54-ball VFBGA (10mm x 12.5mm)
2
54-ball VFBGA (Lead Free)
2
• Timing (Cycle Time)
6.0ns @ CL=3 (167 MHz)
7.5ns @ CL = 3 (133 MHz)
8.0ns @ CL = 3 (125 MHz)
• Operating Temperature
Commercial (0
o
C to + 70
o
C)
Industrial (-40
o
C to + 85
o
C)
MARKING
V
H
32M16
TG
P
FN
BN
-6A
-75
-8
None
IT
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
32 Meg x 16
8 Meg x 16 x 4 banks
8K
8K (A0–A12)
4 (BA0, BA1)
1,024(A0–A9)
KEY TIMING PARAMETERS
SPEED
GRADE
-6A
-75
-8
-75
-8
-8
CLOCK
FREQUENCY
167MHz
133MHz
125MHz
104MHz
104MHz
50MHz
ACCESS TIME
CL=1* CL=2* CL=3*
19ns
6ns
8ns
5.0ns
5.4ns
7ns
SETUP HOLD
TIME TIME
1.5ns
1.5ns
2.5ns
1.5ns
2.5ns
2.5ns
0.8ns
0.8ns
1.0ns
0.8ns
1.0ns
1.0ns
NOTE:
1. Contact Factory for availability.
2. Due to space limitations, FBGA-packaged compo-
nents have an abbreviated part mark that is different
from the part number. See our Web site for more
information on abbreviated component marks at
http://www.micron.com/decoder.
*CL = CAS (READ) latency
09005aef80d053fa
MobileRamY27L_A.p65 – Pub. 07/03
1
©2003 Micron Technology, Inc. All rights reserved.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PUROPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION DATA SHEET SPECIFICATIONS.
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