a
ADSP-2192M DUAL CORE DSP FEATURES
320 MIPS ADSP-219x DSP in a 144-Lead LQFP Package
with PCI, USB, Sub-ISA, and CardBus Interfaces
3.3 V/5.0 V PCI 2.2 Compliant 33 MHz/32-bit Interface
with Bus Mastering over Four DMA Channels with
Scatter-Gather Support
Integrated USB 1.1 Compliant Interface
Sub-ISA Interface
AC’97 Revision 2.1 Compliant Interface for External
Audio, Modem, and Handset Codecs with DMA
Capability
Dual ADSP-219x Core Processors (P0 and P1) on Each
ADSP-2192M DSP Chip
132K Words of Memory Includes 4K 16-Bit Shared
Data Memory
DSP Microcomputer
ADSP-2192M
80K Words of On-Chip RAM on P0, Configured as
64K Words On-Chip 16-Bit RAM for Data Memory and
16K Words On-Chip 24-Bit RAM for Program Memory
48K Words of On-Chip RAM on P1, Configured as
32K Words On-Chip 16-Bit RAM for Data Memory and
16K Words On-Chip 24-Bit RAM for Program Memory
4K Words of Additional On-Chip RAM Shared by Both
Cores, Configured as 4K Words On-Chip 16-Bit RAM
Flexible Power Management with Selectable Power-
Down and Idle Modes
Programmable PLL Supports Frequency Multiplication,
Enabling Full Speed Operation from Low Speed
Input Clocks
2.5 V Internal Operation Supports 3.3 V/5.0 V
Compliant I/O
FUNCTIONAL BLOCK DIAGRAM
P0
MEMORY
16K 24 PM
64K 16 DM
BOOT ROM
ADDR DATA
ADSP-219x
DSP CORE
P1
MEMORY
16K 24 PM
32K 16 DM
BOOT ROM
ADDR DATA
ADSP-219x
DSP CORE
SHARED
MEMORY
4K 16 DM
ADDR DATA
(SEE FIGURE 1
ON PAGE 3)
(SEE FIGURE 1
ON PAGE 3)
CORE
INTERFACE
CORE
INTERFACE
ADDR DATA
ADDR DATA
ADDR DATA
P1 DMA
CONTROLLER
SHARED DSP
I/O MAPPED
REGISTERS
FIFOS
PROCESSOR P0
PROCESSOR P1
P0 DMA
CONTROLLER
FIFOS
GP I/O PINS
(AND
OPTIONAL
SERIAL
EEPROM)
SERIAL PORT
AC'97
COMPLIANT
HOST PORT
PCI 2.2
OR
USB 1.1
JTAG
EMULATION
PORT
REV. 0
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may result from its use. No license is granted by implication or otherwise
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Fax:781/326-8703
©
2002 Analog Devices, Inc. All rights reserved.
ADSP-2192M
ADSP-2192M DUAL CORE DSP FEATURES (continued)
Eight Dedicated General-Purpose I/O Pins with Integrated
Interrupt Support
Each DSP Core Has a Programmable 32-Bit Interval Timer
Five DMA Channels Available on Each Core
Boot Methods Include Booting Through PCI Port, USB
Port, or Serial EEPROM
JTAG Test Access Port Supports On-Chip Emulation and
System Debugging
144-Lead LQFP Package
DSP CORE FEATURES
6.25 ns Instruction Cycle Time (Internal), for up to
160 MIPS Sustained Performance
ADSP-218x Family Code Compatible with the Same Easy
to Use Algebraic Syntax
Single-Cycle Instruction Execution
Dual Purpose Program Memory for Both Instruction and
Data Storage
Fully Transparent Instruction Cache Allows Dual Operand
Fetches in Every Instruction Cycle
Unified Memory Space Permits Flexible Address
Generation, Using Two Independent DAG Units
Independent ALU, Multiplier/Accumulator, and Barrel
Shifter Computational Units with Dual 40-Bit
Accumulators
Single-Cycle Context Switch between Two Sets of
Computational and DAG Registers
Parallel Execution of Computation and Memory
Instructions
Pipelined Architecture Supports Efficient Code Execution
at Speeds up to 160 MIPS
Register File Computations with All Nonconditional,
Nonparallel Computational Instructions
Powerful Program Sequencer Provides Zero-Overhead
Looping and Conditional Instruction Execution
Architectural Enhancements for Compiled C/C++ Code
Efficiency
Architecture Enhancements beyond ADSP-218x Family
are Supported with Instruction Set Extensions for
Added Registers, Ports, and Peripherals
TABLE OF CONTENTS
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . 3
DSP Core Architecture . . . . . . . . . . . . . . . . . . . . . . . 3
DSP Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . 4
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
External Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Internal Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Register Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
CardBus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Using the PCI Interface . . . . . . . . . . . . . . . . . . . . . . . 7
Using the USB Interface . . . . . . . . . . . . . . . . . . . . . 13
General USB Device Definitions . . . . . . . . . . . . . . . 17
Sub-ISA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 21
PCI Interface to DSP Memory . . . . . . . . . . . . . . . . 22
USB Interface to DSP Memory . . . . . . . . . . . . . . . . 22
AC’97 Codec Interface to DSP Memory . . . . . . . . . 22
Data FIFO Architecture . . . . . . . . . . . . . . . . . . . . . 22
System Reset Description . . . . . . . . . . . . . . . . . . . . 23
Power Management Description . . . . . . . . . . . . . . . 24
Power Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.5 V Regulator Options . . . . . . . . . . . . . . . . . . . . . 24
Low Power Operation . . . . . . . . . . . . . . . . . . . . . . . 25
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Instruction Set Description . . . . . . . . . . . . . . . . . . . 26
Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . 26
Additional Information . . . . . . . . . . . . . . . . . . . . . . 28
PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . 28
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . 30
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . 31
ESD SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . 31
TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . 31
Output Drive Currents . . . . . . . . . . . . . . . . . . . . . . 34
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Environmental Conditions . . . . . . . . . . . . . . . . . . . 35
144-Lead LQFP Pinout . . . . . . . . . . . . . . . . . . . . . 36
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . 38
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . 38
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ADSP-2192M
GENERAL DESCRIPTION
The ADSP-2192M is a single-chip microcomputer optimized for
digital signal processing (DSP) and other high speed numeric
processing applications, and is ideally suited for PC peripherals.
The ADSP-2192M combines the ADSP-219x family base archi-
tecture (three computational units, two data address generators
and a program sequencer) into a chip with two core processors
(see the Functional Block Diagram
on Page 1
and
Figure 1).
The ADSP-2192M’s flexible architecture and comprehensive
instruction set support multiple operations in parallel. For
example, in one processor cycle, each DSP core within the
ADSP-2192M can:
•
Generate an address for the next instruction fetch
•
Fetch the next instruction
•
Perform one or two data moves
•
Update one or two data address pointers
•
Perform a computational operation
These operations take place while the processor continues to:
•
Receive and/or transmit data through the Host port (PCI
or USB interfaces)
•
Receive or transmit data through the AC’97
•
Decrement the two timers
DSP Core Architecture
DSP CORE
CACHE
64 24-BIT
4
DAG1
4 16
4
DAG2
4 16
PROGRAM
SEQUENCER
PM ADDRESS BUS
DM ADDRESS BUS
24
24
PM DATA BUS
BUS
CONNECT
(PX)
DATA
REGISTER
FILE
DM DATA BUS
24
16
The ADSP-219x architecture is code compatible with the ADSP-
218x DSP family. Though the architectures are compatible, the
ADSP-219x architecture has many enhancements over the
ADSP-218x architecture. The enhancements to computational
units, data address generators, and program sequencer make the
ADSP-219x more flexible and more compiler friendly.
CORE
INTERFACE
INPUT
REGISTERS
RESULT
REGISTERS
Indirect addressing options provide addressing flexibility: base
address registers for easier implementation of circular buffering,
pre-modify with no update, post-modify with update, pre- and
post-modify by an immediate 8-bit, twos-complement value.
The ADSP-219x instruction set provides flexible data moves and
multifunction (one or two data moves with a computation)
instructions. Every single-word instruction can be executed in a
single processor cycle. The ADSP-219x assembly language uses
an algebraic syntax for ease of coding and readability. A compre-
hensive set of development tools supports program development.
The Functional Block Diagram
on Page 1
shows the architecture
of the ADSP-219x dual core DSP, while the block diagram of
Figure 1
illustrates the ADSP-219x DSP core. Each core
contains three independent computational units: the multi-
plier/accumulator (MAC), the ALU, and the shifter. The
computational units process 16-bit data from the register file and
have provisions to support multiprecision computations. The
ALU performs a standard set of arithmetic and logic operations;
division primitives are also supported. The MAC performs
single-cycle multiply, multiply/add, and multiply/subtract oper-
ations. The MAC has two 40-bit accumulators that help with
overflow. The shifter performs logical and arithmetic shifts, nor-
malization, denormalization, and derive exponent operations.
The shifter can be used to efficiently implement numeric format
control, including multiword and block floating-point
representations.
Register-usage rules influence placement of input and results
within the computational units. For most operations, the com-
putational units’ data registers act as a data register file,
permitting any input or result register to provide input to any unit
for a computation. For feedback operations, the computational
units let the output (result) of any unit be input to any unit on
–3–
MULT
16
16-BIT
BARREL
SHIFTER
ALU
Figure 1. ADSP-219x DSP Core
The ADSP-2192M includes a PCI-compatible port, a USB-
compatible port, an AC’97-compatible port, a DMA controller,
a programmable timer, general-purpose Programmable Flag
pins, extensive interrupt capabilities, and on-chip program and
data memory spaces.
The ADSP-2192M integrates 132K words of on-chip memory
configured as 32K words (24-bit) of program RAM, and 100K
words (16-bit) of data RAM. power-down circuitry is also
provided to reduce power consumption. The ADSP-2192M is
available in a 144-lead LQFP package.
Fabricated in a high speed, low power, CMOS process, the
ADSP-2192M operates with a 6.25 ns instruction cycle time
(320 MIPS) using both cores. All instructions can execute in a
single DSP cycle.
REV. 0
ADSP-2192M
the next cycle. For conditional or multifunction instructions,
there are restrictions on which data registers may provide inputs
or receive results from each computational unit. For more infor-
mation, see the ADSP-219x
DSP Instruction Set Reference.
A powerful program sequencer controls the flow of instruction
execution. The sequencer supports conditional jumps, subrou-
tine calls, and low interrupt overhead. With internal loop
counters and loop stacks, the ADSP-219x core executes looped
code with zero overhead; no explicit jump instructions are
required to maintain loops.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches. Each DAG maintains and
updates four 16-bit address pointers. Whenever the pointer is
used to access data (indirect addressing), it is pre- or post-
modified by the value of one of four possible modify registers. A
length value and base address may be associated with each pointer
to implement automatic modulo addressing for circular buffers.
Page registers in the DAGs allow linear or circular addressing
within 64K word boundaries of each of the memory pages, but
these buffers may not cross page boundaries. Secondary registers
duplicate all the primary registers in the DAGs; switching
between primary and secondary registers provides a fast context
switch.
Efficient data transfer in the core is achieved with the use of
internal buses:
•
Program Memory Address (PMA) Bus
•
Program Memory Data (PMD) Bus
•
Data Memory Address (DMA) Bus
•
Data Memory Data (DMD) Bus
Program memory can store both instructions and data, permit-
ting the ADSP-219x to fetch two operands in a single cycle, one
from program memory and one from data memory. The DSP’s
dual memory buses also let the ADSP-219x core fetch an operand
from data memory and the next instruction from program
memory in a single cycle.
DSP Peripherals
The programmable interval timer generates periodic interrupts.
A 16-bit count register (TCOUNT) is decremented every
n cycles where n-1 is a scaling value stored in a 16-bit register
(TSCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (TPERIOD).
Memory Architecture
The ADSP-2192M provides 132K words of on-chip SRAM
memory. This memory is divided into Program and Data
Memory blocks in each DSP’s memory map. In addition to the
internal memory space, the two cores can address two additional
and separate off-core memory spaces: I/O space and shared
memory space, as shown in
Figure 2.
The ADSP-2192M’s two cores can access 80K and 48K locations
that are accessible through two 24-bit address buses, the PMA
and DMA buses.The DSP has three functions that support access
to the full memory map.
•
The DAGs generate 24-bit addresses for data fetches from
the entire DSP memory address range. Because DAG
index (address) registers are 16 bits wide and hold the
lower 16 bits of the address, each of the DAGs has its own
8-bit page register (DMPGx) to hold the most significant
eight address bits. Before a DAG generates an address,
the program must set the DAG’s DMPGx register to the
appropriate memory page.
•
The Program Sequencer generates the addresses for
instruction fetches. For relative addressing instructions,
the program sequencer bases addresses for relative jumps,
calls, and loops on the 24-bit Program Counter (PC). In
direct addressing instructions (two-word instructions),
the instruction provides an immediate 24-bit address
value. The PC allows linear addressing of the full 24-bit
address range.
•
For indirect jumps and calls that use a 16-bit DAG
address register for part of the branch address, the
Program Sequencer relies on an 8-bit Indirect Jump page
(IJPG) register to supply the most significant eight
address bits. Before a cross page jump or call, the program
must set the program sequencer’s IJPG register to the
appropriate memory page.
Each ADSP-219x DSP core has an on-chip ROM that holds boot
routines (See
Booting Modes on Page 23.).
Interrupts
The Functional Block Diagram on Page 1 shows the DSP’s
on-chip peripherals, which include the Host port (PCI or USB),
AC’97 port, JTAG test and emulation port, flags, and interrupt
controller.
The ADSP-2192M can respond to up to thirteen interrupts at
any given time. A list of these interrupts appears in
Table 2.
The AC’97 Codec port on the ADSP-2192M provides a
complete synchronous, full-duplex serial interface. This interface
supports the AC’97 standard.
The ADSP-2192M provides up to eight general-purpose I/O pins
that are programmable as either inputs or outputs. These pins
are dedicated general-purpose Programmable Flag pins.
The interrupt controller lets the DSP respond to 13 interrupts
with minimum overhead. The controller implements an interrupt
priority scheme as shown in
Table 2.
Applications can use the
unassigned slots for software and peripheral interrupts. The
DSP’s Interrupt Control (ICNTL) register (shown in
Table 3)
provides controls for global interrupt enable, stack interrupt con-
figuration, and interrupt nesting.
–4–
REV. 0
ADSP-2192M
DSP P0
MEMORY MAP
ADDRESS
PAGE 2
SHARED RAM
(16 4K)
RESERVED
0x01 5000
PAGE 1
PROGRAM ROM
24 4K
PROGRAM RAM
(24 16K)
0x01 0000
0x00 FFFF
DATA RAM
BLOCK3
(16 16K)
DATA RAM
BLOCK2
(16 16K)
PAGE 0
DATA RAM
BLOCK1
(16 16K)
0x01 4FFF
0x01 4000
0x01 3FFF
PROGRAM RAM
(24 16K)
0x01 0000
0x00 FFFF
PAGE 1
PROGRAM ROM
24 4K
0x02 0FFF
0x02 0000
0x01 FFFF
RESERVED
0x01 5000
0x01 4FF F
0x01 4000
0x01 3FF F
SAME
PAGE 2
SHARED RAM
(16 4K)
DSP P1
MEMORY MAP
ADDRESS
0x02 0FF F
0x02 0000
0x01 FFFF
0x00 C000
0x00 BFFF
SHARED
DSP I/O
MAPPED
REGISTERS
ADDRESS
0xFF FF
PAGE 0
RESERVED
0x00 8000
0x00 7FFF
0x00 8000
0x00 7FF F
DATA RAM
BLOCK1
(16 16K)
0x00 4000
0x00 3FFF
PAGES 0 255
(16 256)
0x00 4000
0x00 3FF F
DATA RAM
BLOCK0
(16 16K)
0x00 0000
0x00 00
DATA RAM
BLOCK0
(16 16K)
0x00 0000
Figure 2. ADSP-2192M Internal/External Memory, Boot Memory, and I/O Memory Maps
Table 2
shows the interrupt vector and DSP-to-DSP semaphores
at reset of each of the peripheral interrupts. The peripheral inter-
rupt’s position in the IMASK and IRPTL register and its vector
address depend on its priority level, as shown in
Table 2.
Table 1. DSP-to-DSP Semaphores Register Table
Flag
Bit
Direction
Function
Table 2. Vector Table
Vector
Address
Offset
1
Bit
Priority
Interrupt
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
DSP–DSP Semaphore 0
DSP–DSP Semaphore 1
DSP–DSP Interrupt
Reserved
Reserved
Reserved
Reserved
Register Bus Lock
DSP–DSP Semaphore 0
DSP–DSP Semaphore 1
DSP–DSP Interrupt
Reserved
AC’97 Register–PDC Bus Access
Status
PDC Interface Busy Status (write
from DSP pending)
Reserved
Register Bus Lock Status
Reset (non-maskable)
Power-Down (non-
maskable)
Kernel interrupt
(single step)
Stack Status
Mailbox
Timer
GPIO
PCI Bus Master
DSP–DSP
FIFO0 Transmit
FIFO0 Receive
FIFO1 Transmit
FIFO1 Receive
Reserved
Reserved
AC’97 Frame
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
0x20
0x24
0x28
0x2C
0x30
0x34
0x38
0x3C
The interrupt vector address values are represented as offsets from
address 0x01 0000. This address corresponds to the start of Program
Memory in DSP P0 and P1.
REV. 0
–5–
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