ADS5240IPAP datasheet, PDF - EEWORLD Datasheet

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ADS5240IPAP: Description4-CH 12-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQFP64; Categorysemiconductor logic; File Size400KB，24 Pages; ManufacturerBurr-Brown; Websitehttp://www.burr-brown.com/

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ADS5240IPAP Overview

4-CH 12-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQFP64

ADS5240IPAP Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	64
Maximum operating temperature	85 Cel
Minimum operating temperature	-40 Cel
Rated supply voltage	3.3 V
Maximum linear error	0.0488 %
Maximum limit analog input voltage	2.03 V
Minimum limit analog input voltage	0.0 V
Processing package description	green, plastic, HTQFP-64
Lead-free	Yes
EU RoHS regulations	Yes
China RoHS regulations	Yes
state	ACTIVE
Craftsmanship	CMOS
packaging shape	SQUARE
Package Size	FLATPACK, HEAT SINK/SLUG, THIN PROFILE, FINE PITCH
surface mount	Yes
Terminal form	GULL WING
Terminal spacing	0.5000 mm
terminal coating	Nickel Palladium
Terminal location	Four
Packaging Materials	Plastic/Epoxy
Temperature level	INDUSTRIAL
Sampling Rate	40 MHz
Output format	serial
Type of converter	proprietary method
Number of digits	12
Output bit encoding	OFFSET binary
Number of analog channels	4
Sample and hold and track and hold	SAMPLE

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Burr Brown Products

from Texas Instruments

ADS5240

SBAS326C – JUNE 2004 – REVISED DECEMBER 2004

4-Channel, 12-Bit, 40MSPS ADC

with Serial LVDS Interface

FEATURES

•

Maximum Sample Rate: 40MSPS

12-Bit Resolution

No Missing Codes

Power Dissipation: 607mW

CMOS Technology

Simultaneous Sample-and-Hold

70.5dBFS SNR at 10MHz IF

Internal and External References

3.3V Digital/Analog Supply

Serialized LVDS Outputs

Integrated Frame and Bit Patterns

MSB and LSB First Modes

Option to Double LVDS Clock Output Currents

Pin- and Format-Compatible Family

HTQFP-64 PowerPAD™ Package

An integrated phase lock loop multiplies the incoming

ADC sampling clock by a factor of 12. This 12x clock

is used in the process of serializing the data output

from each channel. The 12x clock is also used to

generate a 1x and a 6x clock, both of which are

transmitted as LVDS clock outputs. The 6x clock is

denoted by the differential pair LCLK

and LCLK

while the 1x clock is denoted by ADCLK

and

ADCLK

. The word output of each ADC channel can

be transmitted either as MSB or LSB first. The bit

coinciding with the rising edge of the 1x clock output

is the first bit of the word. Data is to be latched by the

receiver on both the rising and falling edges of the 6x

clock.

The ADS5240 provides internal references, or can

optionally be driven with external references. Best

performance can be achieved through the internal

reference mode.

The device is available in an HTQFP-64 PowerPAD

package and is specified over a -40°C to +85°C

operating range.

6X ADCLK

LCLK

PLL

ADCLK

ADC LK

APPLICATIONS

Portable Ultrasound Systems

Tape Drives

Test Equipment

Optical Networking

1X ADCLK

DESCRIPTION

The ADS5240 is a high-performance, 4-channel,

40MSPS analog-to-digital converter (ADC). Internal

references are provided, simplifying system design

requirements. Low power consumption allows for the

highest of system integration densities. Serial LVDS

(low-voltage differential signaling) outputs reduce the

number of interface lines and package size.

ADS5240IPAP Related Products

	ADS5240IPAP	ADS5240	ADS5240IPAPT	ADS5240IPAPG4	ADS5240IPAPTG4
Description	4-CH 12-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQFP64	4-Channel, 12-Bit, 40MSPS ADC with Serial LVDS Interface	4-CH 12-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQFP64	4-CH 12-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQFP64	4-CH 12-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQFP64
Number of functions	1	-	1	1	1
Number of terminals	64	-	64	64	64
Maximum operating temperature	85 Cel	-	85 Cel	85 Cel	85 Cel
Minimum operating temperature	-40 Cel	-	-40 Cel	-40 Cel	-40 Cel
Rated supply voltage	3.3 V	-	3.3 V	3.3 V	3.3 V
Maximum linear error	0.0488 %	-	0.0488 %	0.0488 %	0.0488 %
Maximum limit analog input voltage	2.03 V	-	2.03 V	2.03 V	2.03 V
Minimum limit analog input voltage	0.0 V	-	0.0 V	0.0 V	0.0 V
Processing package description	green, plastic, HTQFP-64	-	green, plastic, HTQFP-64	green, plastic, HTQFP-64	green, plastic, HTQFP-64
Lead-free	Yes	-	Yes	Yes	Yes
EU RoHS regulations	Yes	-	Yes	Yes	Yes
China RoHS regulations	Yes	-	Yes	Yes	Yes
state	ACTIVE	-	ACTIVE	ACTIVE	ACTIVE
Craftsmanship	CMOS	-	CMOS	CMOS	CMOS
packaging shape	SQUARE	-	SQUARE	SQUARE	SQUARE
Package Size	FLATPACK, HEAT SINK/SLUG, THIN PROFILE, FINE PITCH	-	FLATPACK, HEAT SINK/SLUG, THIN PROFILE, FINE PITCH	FLATPACK, HEAT SINK/SLUG, THIN PROFILE, FINE PITCH	FLATPACK, HEAT SINK/SLUG, THIN PROFILE, FINE PITCH
surface mount	Yes	-	Yes	Yes	Yes
Terminal form	GULL WING	-	GULL WING	GULL WING	GULL WING
Terminal spacing	0.5000 mm	-	0.5000 mm	0.5000 mm	0.5000 mm
terminal coating	Nickel Palladium	-	Nickel Palladium	Nickel Palladium	Nickel Palladium
Terminal location	Four	-	Four	Four	Four
Packaging Materials	Plastic/Epoxy	-	Plastic/Epoxy	Plastic/Epoxy	Plastic/Epoxy
Temperature level	INDUSTRIAL	-	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Sampling Rate	40 MHz	-	40 MHz	40 MHz	40 MHz
Output format	serial	-	serial	serial	serial
Type of converter	proprietary method	-	proprietary method	proprietary method	proprietary method
Number of digits	12	-	12	12	12
Output bit encoding	OFFSET binary	-	OFFSET binary	OFFSET binary	OFFSET binary
Number of analog channels	4	-	4	4	4
Sample and hold and track and hold	SAMPLE	-	SAMPLE	SAMPLE	SAMPLE

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