Burr Brown Products
from Texas Instruments
ADS5240
¨
SBAS326C – JUNE 2004 – REVISED DECEMBER 2004
4-Channel, 12-Bit, 40MSPS ADC
with Serial LVDS Interface
FEATURES
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Maximum Sample Rate: 40MSPS
12-Bit Resolution
No Missing Codes
Power Dissipation: 607mW
CMOS Technology
Simultaneous Sample-and-Hold
70.5dBFS SNR at 10MHz IF
Internal and External References
3.3V Digital/Analog Supply
Serialized LVDS Outputs
Integrated Frame and Bit Patterns
MSB and LSB First Modes
Option to Double LVDS Clock Output Currents
Pin- and Format-Compatible Family
HTQFP-64 PowerPAD™ Package
An integrated phase lock loop multiplies the incoming
ADC sampling clock by a factor of 12. This 12x clock
is used in the process of serializing the data output
from each channel. The 12x clock is also used to
generate a 1x and a 6x clock, both of which are
transmitted as LVDS clock outputs. The 6x clock is
denoted by the differential pair LCLK
P
and LCLK
N
,
while the 1x clock is denoted by ADCLK
P
and
ADCLK
N
. The word output of each ADC channel can
be transmitted either as MSB or LSB first. The bit
coinciding with the rising edge of the 1x clock output
is the first bit of the word. Data is to be latched by the
receiver on both the rising and falling edges of the 6x
clock.
The ADS5240 provides internal references, or can
optionally be driven with external references. Best
performance can be achieved through the internal
reference mode.
The device is available in an HTQFP-64 PowerPAD
package and is specified over a -40°C to +85°C
operating range.
6X ADCLK
LCLK
P
LCLK
N
PLL
ADCLK
ADC LK
P
ADC LK
N
APPLICATIONS
Portable Ultrasound Systems
Tape Drives
Test Equipment
Optical Networking
1X ADCLK
DESCRIPTION
The ADS5240 is a high-performance, 4-channel,
40MSPS analog-to-digital converter (ADC). Internal
references are provided, simplifying system design
requirements. Low power consumption allows for the
highest of system integration densities. Serial LVDS
(low-voltage differential signaling) outputs reduce the
number of interface lines and package size.
RELATED PRODUCTS
MODEL
ADS5242
(1)
RESOLUTION
(BITS)
12
SAMPLE RATE
(MSPS)
65
CHANNELS
4
IN1
P
IN1
N
IN2
P
IN2
N
IN3
P
IN3
N
IN4
P
IN4
N
S/H
S/H
S/H
S/H
12− Bit
ADC
Serializer
OUT 1
P
OUT 1
N
OUT 2
P
OUT 2
N
OUT 3
P
OUT 3
N
OUT 4
P
OUT 4
N
12− Bit
ADC
Serializer
12− Bit
ADC
Serializer
12− Bit
ADC
Serializer
Reference
Registers
Control
(1) Available Q1 2005.
RESET
SCLK
SDATA
REF
T
V
C M
REF
B
CS
INT/EXT
PD
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004, Texas Instruments Incorporated
ADS5240
SBAS326C – JUNE 2004 – REVISED DECEMBER 2004
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
ORDERING INFORMATION
(1)
PACKAGE
DESIGNATOR
PAP
SPECIFIED
TEMPERATURE
RANGE
-40°C to +85°C
PACKAGE
MARKING
ADS5240I
ORDERING
NUMBER
ADS5240IPAP
ADS5240IPAPT
TRANSPORT
MEDIA, QUANTITY
Tray, 160
Tape and Reel, 1000
PRODUCT
ADS5240
(1)
(2)
PACKAGE-LEAD
HTQFP-64
(2)
For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet.
Thermal pad size: 5.29mm
×
5.29mm (min), 6.50mm
×
6.50mm (max).
ABSOLUTE MAXIMUM RATINGS
(1)
Supply Voltage Range, AVDD
Supply Voltage Range, LVDD
Voltage Between AVSS and LVSS
Voltage Between AVDD and LVDD
Voltage Applied to External REF Pins
All LVDS Data and Clock Outputs
Analog Input Pins
Peak Total Input Current (all inputs)
Junction Temperature
Operating Free-Air Temperature Range, T
A
Lead Temperature, 1.6mm (1/16" from case for 10s)
(1)
-0.3V to +3.8V
-0.3V to +3.8V
-0.3V to +0.3V
-0.3V to +0.3V
-0.3V to +2.4V
-0.3V to +2.4V
-0.15V to +3.0V
30mA
+105°C
-40°C to +85°C
220°C
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
2
ADS5240
www.ti.com
SBAS326C – JUNE 2004 – REVISED DECEMBER 2004
RECOMMENDED OPERATING CONDITIONS
ADS5240
MIN
SUPPLIES AND REFERENCES
Analog Supply Voltage, AVDD
Output Driver Supply Voltage, LVDD
CLOCK INPUT AND OUTPUTS
ADCLK Input Sample Rate (low-voltage TTL)
Low-Level Voltage Clock Input
High-Level Voltage Clock Input
ADCLK
P
and ADCLK
N
Outputs (LVDS)
LCLK
P
and LCLK
N
Outputs (LVDS)
(1)
Operating Free-Air Temperature, T
A
Thermal Characteristics:
θ
JA
θ
JC
(1)
6
×
ADCLK.
24
15
°C/W
°C/W
2.2
20
120
-40
40
240
+85
20
40
0.6
MSPS
V
V
MHz
MHz
°C
3.0
3.0
3.3
3.3
3.6
3.6
V
V
TYP
MAX
UNITS
REFERENCE SELECTION
MODE
Internal Reference
External Reference
INT/EXT DESCRIPTION
1
0
Full-scale range = 2.0V
PP
. Default with internal pull-up.
Internal reference is powered down. Common mode of external reference should be within
50mV of V
CM
. V
CM
is derived from the internal bandgap voltage.
3
ADS5240
SBAS326C – JUNE 2004 – REVISED DECEMBER 2004
www.ti.com
ELECTRICAL CHARACTERISTICS
T
MIN
= -40°C and T
MAX
= +85°C. Typical values are at T
A
= 25°C, clock frequency = 40MSPS, 50% clock duty cycle,
AVDD = 3.3V, LVDD = 3.3V differential, transformer coupled inputs, -1dBFS, I
SET
= 56.2kΩ, internal voltage reference, and
LDVS buffer current at 3.5mA per channel, unless otherwise noted.
ADS5240
PARAMETER
DC ACCURACY
No Missing Codes
DNL Differential Nonlinearity
INL Integral Nonlinearity
Offset Error
(1)
Offset Temperature Coefficient
Fixed Attenuation in
Gain
Error
(4)
Channel
(2)
REF
T
- REF
B
-5
Variable Attenuation in Channel
(3)
Attenuation Temperature
Coefficient
(5)
POWER SUPPLY
I
CC
Total Supply Current
I(AVDD) Analog Supply Current
I(LVDD) Digital Output Driver Supply Current
Power Dissipation
Power-Down
REFERENCE VOLTAGES
VREF
T
Reference Top (internal)
VREF
B
Reference Bottom (internal)
V
CM
Common-Mode Voltage
V
CM
Output Current
(6)
VREF
T
Reference Top (external)
VREF
B
Reference Bottom (external)
External Reference Input
ANALOG INPUT
Differential Input Capacitance
Analog Input Common-Mode Range
Differential Input Voltage Range
Voltage Overhead Recovery Time
Input Bandwidth
DIGITAL DATA OUTPUTS
Data Bit Rate
(1)
(2)
240
480
MBPS
Differential Input Signal at 4V
PP
Recovery to Within 1% of Code
-3dBFS
1.5
4.0
300
4.0
V
CM
±
0.05
2.02
pF
V
V
PP
CLK Cycles
MHz
Current
(7)
1.0
±50mV
Change in Voltage
1.875
1.125
1.95
0.95
1.45
2.0
1.0
1.5
±2
2.05
1.05
1.55
V
V
V
mA
V
V
mA
Clock Running
V
IN
= FS, F
IN
= 5MHz
V
IN
= FS, F
IN
= 5MHz
V
IN
= FS, F
IN
= 5MHz,
LVDS into 100Ω Load
184
142
42
607
95
650
mA
mA
mA
mW
mW
f
IN
= 5MHz
f
IN
= 5MHz
-0.9
-2.0
-0.75
Assured
±0.4
±0.75
±0.2
14
1
±0.2
±1.0
44
+5
+0.9
+2.0
+0.75
LSB
LSB
%FS
ppm/°C
%FS
%FS
%FS
ppm/°C
TEST CONDITIONS
MIN
TYP
MAX
UNITS
(3)
(4)
(5)
(6)
(7)
4
Offset error is the deviation of the average code from mid-code for a zero input. Offset error is expressed in terms of % of full-scale.
Fixed attenuation in the channel arises due to a fixed attenuation of about 1% in the sample-and-hold amplifier. When the differential
voltage at the analog input pins are changed from -V
REF
to +V
REF
, the swing of the output code is expected to deviate from the full-scale
code (4096LSB) by the extent of this fixed attenuation.
NOTE: V
REF
is defined as (REF
T
- REF
B
).
Variable attenuation in the channel refers to the attenuation of the signal in the channel over and above the fixed attenuation.
The reference voltages are trimmed at production so that (VREF
T
- VREF
B
) is within
±
50mV of the ideal value of 1V. It does not include
fixed attenuation.
The attenuation temperature coefficient refers to the temperature coefficient of the attenuation in the channel. It does not account for the
variation of the reference voltages with temperature.
V
CM
provides the common-mode current for the inputs of all four channels when the inputs are AC-coupled. The V
CM
output current
specified is the additional drive of the V
CM
buffer if loaded externally.
Average current drawn from the reference pins in the external reference mode.
ADS5240
www.ti.com
SBAS326C – JUNE 2004 – REVISED DECEMBER 2004
AC CHARACTERISTICS
T
MIN
= -40°C and T
MAX
= +85°C. Typical values are at T
A
= 25°C, clock frequency = 40MSPS, 50% clock duty cycle,
AVDD = 3.3V, LVDD = 3.3V differential, transformer coupled inputs, -1dBFS, I
SET
= 56.2kΩ, internal voltage reference, and
LVDS buffer current at 3.5mA per channel, unless otherwise noted.
ADS5240
PARAMETER
DYNAMIC CHARACTERISTICS
f
IN
= 1MHz
SFDR Spurious-Free Dynamic Range
f
IN
= 5MHz
f
IN
= 10MHz
f
IN
= 1MHz
HD
2
2nd-Order Harmonic Distortion
f
IN
= 5MHz
f
IN
= 10MHz
f
IN
= 1MHz
HD
3
3rd-Order Harmonic Distortion
f
IN
= 5MHz
f
IN
= 10MHz
f
IN
= 1MHz
SNR Signal-to-Noise Ratio
f
IN
= 5MHz
f
IN
= 10MHz
f
IN
= 1MHz
SINAD Signal-to-Noise and Distortion
f
IN
= 5MHz
f
IN
= 10MHz
IMD Two-Tone Intermodulation Distortion
ENOB Effective Number of Bits
Crosstalk
f
1
= 9.5MHz at -7dBFS
f
2
= 10.2MHz at -7dBFS
f
IN
= 5MHz
Signal Applied to 3 Channels; Measurement Taken
on the Channel with No Input Signal
67
68
78
85
78
87
85
85
95
95
90
87
85
85
70.5
70.5
70
70
70
69.5
-88
11.3
-90
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBc
Bits
dBc
CONDITIONS
MIN
TYP
MAX
UNITS
5
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