DEMO KIT AVAILABLE
DS3150
3.3V DS3/E3/STS-1
Line Interface Unit
www.maxim-ic.com
GENERAL DESCRIPTION
The DS3150 performs all the functions necessary for
interfacing at the physical layer to DS3, E3, and
STS-1 lines. The receiver performs clock and data
recovery, B3ZS/HDB3 decoding, and loss-of-signal
monitoring. The transmitter encodes outgoing data
and drives standards-compliant waveforms onto 75Ω
coaxial cable. The jitter attenuator can be mapped
into the receive path or the transmit path.
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FEATURES
Integrated Transmitter, Receiver, and Jitter
Attenuator for DS3, E3, and STS-1
Performs Receive Clock/Data Recovery and
Transmit Waveshaping
Jitter Attenuator Can Be Placed in the Receive
Path or the Transmit Path
AGC/Equalizer Block Handles from 0dB to
15dB of Cable Loss
Interfaces to 75W Coaxial Cable at Lengths Up to
380m (DS3), 440m (E3), or 360m (STS-1)
Interfaces Directly to a DSX Monitor Signal
(20dB Flat Loss) Using Built-In Preamp
Built-In B3ZS and HDB3 Encoder/Decoder
Bipolar and NRZ Interfaces
Local and Remote Loopbacks
On-Board 2
15
- 1 and 2
23
- 1 Pseudorandom Bit
Sequence (PRBS) Generator and Detector
Line Build-Out (LBO) Control
Transmit Line-Driver Monitor Checks for a
Faulty Transmitter or a Shorted Output
Complete DS3 AIS Generator (ANSI T1.107)
Unframed All-Ones Generator (E3 AIS)
Clock Inversion for Glueless Interfacing
Tri-State Line Driver for Low-Power Mode and
Protection Switching Applications
Loss-of-Signal (LOS) Detector (ANSI T1.231
and ITU G.775)
Requires Minimal External Components
Drop-In Replacement for TDK 78P2241/B and
78P7200L (Refer to
Application Note 362)
Pin Compatible with TDK 78P7200
3.3V Operation (5V Tolerant I/O), 110mA (max)
Industrial Temperature Range: -40°C to +85°C
Small Packaging: 28-Pin PLCC and 48-Pin
TQFP
APPLICATIONS
SONET/SDH and PDH Multiplexers
Digital Cross-Connects
Access Concentrators
ATM and Frame Relay Equipment
Routers
PBXs
DSLAMs
CSUs/DSUs
ORDERING INFORMATION
PART
DS3150QN
DS3150Q
DS3150TN
DS3150T
TEMP RANGE
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
PIN-PACKAGE
28 PLCC
28 PLCC
48 TQFP
48 TQFP
FUNCTIONAL DIAGRAM
LINE IN
DS3, E3,
STS-1
RX+
RX-
RCLK
RPOS
RNEG
RECEIVE
CLOCK
AND DATA
DS3150
LIU
LINE OUT
DS3, E3,
STS-1
TX+
TX-
TCLK
TPOS
TNEG
TRANSMIT
CLOCK
AND DATA
Pin Configurations appear at end of data sheet.
Note:
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:
www.maxim-ic.com/errata.
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010703
DS3150
TABLE OF CONTENTS
1.
1.1
1.2
1.3
1.4
DETAILED DESCRIPTION.................................................................................................4
R
ECEIVER
.................................................................................................................................... 7
T
RANSMITTER
.............................................................................................................................10
D
IAGNOSTICS
..............................................................................................................................15
J
ITTER
A
TTENUATOR
...................................................................................................................16
2.
3.
4.
5.
PIN DESCRIPTIONS ........................................................................................................17
ELECTRICAL CHARACTERISTICS ................................................................................21
PIN CONFIGURATIONS ..................................................................................................25
PACKAGE INFORMATION..............................................................................................26
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DS3150
LIST OF FIGURES
Figure 1-1. Block Diagram ...........................................................................................................4
Figure 1-2. External Connections.................................................................................................6
Figure 1-3. Receiver Jitter Tolerance...........................................................................................9
Figure 1-4. E3 Waveform Template ...........................................................................................13
Figure 1-5. DS3 AIS Structure ...................................................................................................14
Figure 1-6. PRBS Output with Normal RCLK Operation ............................................................15
Figure 1-7. PRBS Output with Inverted RCLK Operation...........................................................15
Figure 1-8. Jitter Attenuation and Jitter Transfer........................................................................16
Figure 3-1. Framer Interface Timing Diagram ............................................................................22
LIST OF TABLES
Table 1-A. Applicable Telecommunications Standards................................................................5
Table 1-B. Transformer Recommendations .................................................................................6
Table 1-C. DS3 Waveform Template .........................................................................................11
Table 1-D. DS3 Waveform Test Parameters and Limits ............................................................11
Table 1-E. STS-1 Waveform Template ......................................................................................12
Table 1-F. STS-1 Waveform Test Parameters and Limits .........................................................12
Table 1-G. E3 Waveform Test Parameters and Limits...............................................................13
Table 2-A. Pin Descriptions........................................................................................................17
Table 2-B. Transmit Data Selection ...........................................................................................20
Table 2-C. RMON and
TTS
Signal Decode ................................................................................20
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DS3150
1. DETAILED DESCRIPTION
The DS3150 performs all the functions necessary for interfacing at the physical layer to DS3, E3, and
STS-1 lines. The device has independent receive and transmit paths and a built-in jitter attenuator
(Figure
1-1).
The receiver performs clock and data recovery from a B3ZS- or HDB3-coded alternate mark
inversion (AMI) signal and monitors for loss-of-signal. The receiver optionally performs B3ZS/HDB3
decoding and outputs the recovered data in either NRZ or bipolar format. The transmitter accepts data in
either NRZ or bipolar format, optionally performs B3ZS/HDB3 encoding, and drives standards-compliant
waveforms onto the outgoing 75Ω coaxial cable. The jitter attenuator can be mapped into the receiver
data path, mapped into the transmitter data path, or disabled. The DS3150 conforms to the
telecommunication standards listed in
Table 1-A. Figure 1-2
shows the external components required for
proper operation.
Figure 1-1. Block Diagram
RMON
MCLK
LOS
Output Decode
PRBS
DS3150
Digital Loss Of
Signal Detector
PRBS
Detector
Pre
Amp
RX-
(Analog
Loss Of
Signal
Detect)
Clock &
Data
Recovery
Jitter Attenuator
(can be placed in either the receive path or the transmit path)
mux
RX+
Filter/
Equalizer
B3ZS/HDB3
Decoder
RPOS/RNRZ
RNEG/RLCV
Clock
Invert
Remote
Loopback
RCLK
Squelch
Analog
Loopback
DM
ZCSE
ICE
TESS
TNEG
TPOS/TNRZ
Clock
Invert
Mux
Driver
Monitor
TX+
Line
Driver
TX-
Wave-
Shaping
Mux
TCLK
B3ZS/
HDB3
Encoder
Loopback Control
Power
Connections
Test Functions
AIS/
1010.../
PRBS
Generation
TTS
LBKS
LBO
VDD
VSS
EFE
TDS0
TDS1
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DS3150
Table 1-A. Applicable Telecommunications Standards
SPECIFICATION
T1.102-1993
T1.107-1995
T1.231-1997
T1.404-1994
G.703
G.751
G.775
G.823
G.824
O.151
ETS 300 686
ETS 300 687
ETS EN 300 689
SPECIFICATION TITLE
ANSI
Digital Hierarchy—Electrical Interfaces
Digital Hierarchy—Formats Specification
Digital Hierarchy—Layer 1 In-Service Digital Transmission Performance
Monitoring
Network-to-Customer Installation—DS3 Metallic Interface Specification
ITU-T
Physical/Electrical Characteristics of Hierarchical Digital Interfaces,
1991
Digital Multiplex Equipment Operating at the Third-Order Bit Rate of 34,368kbps
and the Fourth-Order Bit Rate of 139,264kbps and Using Positive Justification,
1993
Loss-of-Signal (LOS) and Alarm Indication Signal (AIS) Defect Detection and
Clearance Criteria,
November 1994
The Control of Jitter and Wander Within Digital Networks Which are Based on
the 2048kbps Hierarchy,
1993
The Control of Jitter and Wander Within Digital Networks Which are Based on
the 1544kbps Hierarchy,
1993
Error Performance Measuring Equipment Operating at the Primary Rate and
Above,
October 1992
ETSI
Business TeleCommunications; 34Mbps and 140Mbps digital leased lines (D34U,
D34S, D140U, and D140S); Network interface presentation, 1996
Business TeleCommunications; 34Mbps digital leased lines (D34U and D34S);
Connection characteristics,
1996
Access and Terminals (AT); 34Mbps digital leased lines (D34U and D34S);
Terminal equipment interface,
July 2001
Business TeleCommunications; 34Mbps digital unstructured and structured lease
lines; attachment requirements for terminal equipment interface,
1997
Telcordia
SONET Transport Systems: Common Generic Criteria,
Issue 2, December 1995
Transport Systems Generic Requirements (TSGR): Common Requirements,
Issue
2, December 1998
TBR 24
GR-253-CORE
GR-499-CORE
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Automotive Electronics
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