93AA46A/B/C, 93LC46A/B/C,
93C46A/B/C
1K Microwire Compatible Serial EEPROM
Device Selection Table
Part Number
93AA46A
93AA46B
93LC46A
93LC46B
93C46A
93C46B
93AA46C
93LC46C
93C46C
V
CC
Range
1.8-5.5
1.8-5-5
2.5-5.5
2.5-5.5
4.5-5.5
4.5-5.5
1.8-5.5
2.5-5.5
4.5-5.5
ORG Pin
No
No
No
No
No
No
Yes
Yes
Yes
Word Size
8-bit
16-bit
8-bit
16-bit
8-bit
16-bit
8 or 16-bit
8 or 16-bit
8 or 16-bit
Temp Ranges
I
I
I, E
I, E
I, E
I, E
I
I, E
I, E
Packages
P, SN, ST, MS, OT
P, SN, ST, MS, OT
P, SN, ST, MS, OT
P, SN, ST, MS, OT
P, SN, ST, MS, OT
P, SN, ST, MS, OT
P, SN, ST, MS
P, SN, ST, MS
P, SN, ST, MS
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Low-power CMOS technology
ORG pin to select word size for ‘46C version
128 x 8-bit organization ‘A’ ver. devices (no ORG)
64 x 16-bit organization ‘B’ ver. devices (no ORG)
Self-timed ERASE/WRITE cycles (including
auto-erase)
Automatic ERAL before WRAL
Power-on/off data protection circuitry
Industry standard 3-wire serial I/O
Device Status signal (READY/BUSY)
Sequential READ function
1,000,000 E/W cycles
Data retention > 200 years
Temperature ranges supported
- Industrial (I)
- Automotive (E)
-40°C to +85°C
-40°C to +125°C
Description
The Microchip Technology Inc. 93XX46A/B/C devices
are 1K bit low voltage serial Electrically Erasable
PROMs (EEPROM). Word-selectable devices such as
the 93AA46C, 93LC46C or 93C46C are dependent
upon external logic levels driving the ORG pin to set
word size. For dedicated 8-bit communication, the
93AA46A, 93LC46A or 93C46A devices are available,
while the 93AA46B, 93LC46B and 93C46B devices
provide dedicated 16-bit communication. Advanced
CMOS technology makes these devices ideal for low
power, nonvolatile memory applications. The entire
93XX Series is available in standard packages includ-
ing 8-lead PDIP and SOIC, and advanced packaging
including 8-lead MSOP, 6-lead SOT-23, and 8-lead
TSSOP. Pb-free (Pure Matte Sn) finish is also
available.
Package Types (not to scale)
ROTATED SOIC
(ex: 93LC46BX)
PDIP/SOIC
(P, SN)
CS
CLK
DI
DO
1
2
3
4
8
7
6
5
V
CC
NC
ORG*
V
SS
Pin Function Table
Name
CS
CLK
DI
DO
V
SS
NC
ORG
V
CC
Function
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
No internal connection
Memory Configuration
Power Supply
CS
CLK
DI
DO
NC
V
CC
CS
CLK
1
2
3
4
8
7
6
5
ORG*
V
SS
DO
DI
TSSOP/MSOP
(ST, MS)
1
2
3
4
8
7
6
5
V
CC
NC
ORG*
V
SS
DO
V
SS
DI
SOT-23
(OT)
1
2
3
6
5
4
V
CC
CS
CLK
* ORG pin is NC on A/B devices
2003 Microchip Technology Inc.
DS21749D-page 1
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(†)
V
CC
.............................................................................................................................................................................7.0V
All inputs and outputs w.r.t. V
SS
......................................................................................................... -0.6V to V
CC
+1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied ................................................................................................-40°C to +125°C
ESD protection on all pins
......................................................................................................................................................≥
4 kV
† NOTICE:
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
V
CC
= range by device (see Table on Page 1)
Industrial (I):
T
A
= -40°C to +85°C
Automotive (E): T
A
= -40°C to +125°C
Min
2.0
0.7 V
CC
-0.3
-0.3
—
—
2.4
V
CC
- 0.2
—
—
—
—
—
—
—
—
—
—
Typ
—
—
—
—
—
—
—
—
—
—
—
—
500
—
—
100
—
—
Max
V
CC
+1
V
CC
+1
0.8
0.2 V
CC
0.4
0.2
—
—
±1
±1
7
2
—
1
500
—
1
5
Units
V
V
V
V
V
V
V
V
µA
µA
pF
mA
µA
mA
µA
µA
µ
A
µA
Conditions
V
CC
≥
2.7V
V
CC
<
2.7V
V
CC
≥
2.7V
V
CC
<
2.7V
I
OL
= 2.1 mA, V
CC
= 4.5V
I
OL
= 100
µA,
V
CC
= 2.5V
I
OH
= -400
µA,
V
CC
= 4.5V
I
OH
= -100
µA,
V
CC
= 2.5V
V
IN
= V
SS
to V
CC
V
OUT
= V
SS
to V
CC
V
IN
/V
OUT
= 0V
(Note 1)
T
A
= 25°C, F
CLK
= 1 MHz
F
CLK
= 3 MHz, V
CC
= 5.5V
F
CLK
= 2 MHz, V
CC
= 2.5V
F
CLK
= 3 MHz, V
CC
= 5.5V
F
CLK
= 2 MHz, V
CC
= 3.0V
F
CLK
= 2 MHz, V
CC
= 2.5V
I-Temp
E-Temp
CLK = CS = 0V
ORG = DI = V
SS
or V
CC
(Note 2) (N
OTE
3)
(Note 1)
All parameters apply over the specified ranges
unless otherwise noted.
Param. No. Symbol
D1
D2
D3
D4
D5
D6
D7
D8
D9
V
IH
1
V
IH
2
V
IL
1
V
IL
2
V
OL
1
V
OL
2
V
OH
1
V
OH
2
I
LI
I
LO
C
IN
,
C
OUT
I
CC
write
Parameter
High-level input voltage
Low-level input voltage
Low-level output voltage
High-level output voltage
Input leakage current
Output leakage current
Pin capacitance
(all inputs/outputs)
Write current
I
CC
read Read current
D10
I
CCS
Standby current
D11
V
POR
V
CC
voltage detect
93AA46A/B/C, 93LC46A/B/C
93C46A/B/C
—
—
1.5V
3.8V
—
—
V
V
Note 1:
This parameter is periodically sampled and not 100% tested.
2:
ORG pin not available on ‘A’ or ‘B’ versions.
3:
READY/BUSY status must be cleared from DO, see
Section 3.4 "Data Out (DO)".
DS21749D-page 2
2003 Microchip Technology Inc.
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
TABLE 1-2:
AC CHARACTERISTICS
V
CC
= range by device (see Table on Page 1)
Industrial (I):
T
A
= -40°C to +85°C
Automotive (E): T
A
= -40°C to +125°C
Min
—
Max
3
2
1
—
Units
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Conditions
4.5V
≤
V
CC
<
5.5V, 93XX46C only
2.5V
≤
V
CC
<
5.5V
1.8V
≤
V
CC
<
2.5V
4.5V
≤
V
CC
<
5.5V, 93XX46C only
2.5V
≤
V
CC
<
5.5V
1.8V
≤
V
CC
<
2.5V
4.5V
≤
V
CC
<
5.5V, 93XX46C only
2.5V
≤
V
CC
<
5.5V
1.8V
≤
V
CC
<
2.5V
4.5V
≤
V
CC
<
5.5V
2.5V
≤
V
CC
<
4.5V
1.8V
≤
V
CC
<
2.5V
1.8V
≤
V
CC
<
5.5V
1.8V
≤
V
CC
<
5.5V
4.5V
≤
V
CC
<
5.5V, 93XX46C only
2.5V
≤
V
CC
<
5.5V
1.8V
≤
V
CC
<
2.5V
4.5V
≤
V
CC
<
5.5V, 93XX46C only
2.5V
≤
V
CC
<
5.5V
1.8V
≤
V
CC
<
2.5V
4.5V
≤
V
CC
<
5.5V, C
L
= 100 pF
2.5V
≤
V
CC
<
4.5V, C
L
= 100 pF
1.8V
≤
V
CC
<
2.5V, C
L
= 100 pF
4.5V
≤
V
CC
<
5.5V,
(Note 1)
1.8V
≤
V
CC
<
4.5V,
(Note 1)
4.5V
≤
V
CC
<
5.5V, C
L
= 100 pF
2.5V
≤
V
CC
<
4.5V, C
L
= 100 pF
1.8V
≤
V
CC
<
2.5V, C
L
= 100 pF
Erase/Write mode (AA and LC
versions)
Erase/Write mode (93C versions)
ERAL mode, 4.5V
≤
V
CC
≤
5.5V
WRAL mode, 4.5V
≤
V
CC
≤
5.5V
All parameters apply over the specified
ranges unless otherwise noted.
Param. No. Symbol
A1
F
CLK
Parameter
Clock frequency
A2
T
CKH
Clock high time
200
250
450
100
200
450
50
100
250
0
250
50
100
250
50
100
250
—
—
—
—
—
—
A3
T
CKL
Clock low time
—
A4
T
CSS
Chip Select setup time
—
A5
A6
A7
T
CSH
T
CSL
T
DIS
Chip Select hold time
Chip Select low time
Data input setup time
—
—
—
A8
T
DIH
Data input hold time
—
ns
A9
T
PD
Data output delay time
200
250
400
100
200
200
300
500
6
2
6
15
—
ns
A10
A11
T
CZ
T
SV
Data output disable time
Status valid time
ns
ns
A12
A13
A14
A15
A16
T
WC
T
WC
T
EC
T
WL
—
Program cycle time
—
—
—
—
ms
ms
ms
ms
Endurance
1M
cycles 25°C, V
CC
= 5.0V,
(Note 2)
Note 1:
This parameter is periodically sampled and not 100% tested.
2:
This application is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which may be obtained from www.microchip.com.
2003 Microchip Technology Inc.
DS21749D-page 3
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
FIGURE 1-1:
CS
V
IH
V
IL
V
IH
CLK
V
IL
T
DIS
V
IH
DI
V
IL
T
PD
DO
(READ)
V
OH
V
OL
T
CZ
T
SV
STATUS VALID
T
PD
T
CZ
T
DIH
T
CSS
T
CKH
T
CKL
T
CSH
SYNCHRONOUS DATA TIMING
DO V
OH
(PROGRAM)
V
OL
Note:
T
SV
is relative to CS.
TABLE 1-3: INSTRUCTION SET FOR X 16 ORGANIZATION (93XX46B OR 93XX46C WITH ORG = 1)
Instruction
ERASE
ERAL
EWDS
EWEN
READ
WRITE
WRAL
SB
1
1
1
1
1
1
1
Opcode
11
00
00
00
10
01
00
A5
1
0
1
A5
A5
0
A4
0
0
1
A4
A4
1
Address
A3
X
X
X
A3
A3
X
A2
X
X
X
A2
A2
X
A1
X
X
X
A1
A1
X
A0
X
X
X
A0
A0
X
Data In
—
—
—
—
—
D15 - D0
D15 - D0
Data Out
(RDY/BSY)
(RDY/BSY)
HIGH-Z
HIGH-Z
D15 - D0
(RDY/BSY)
(RDY/BSY)
Req. CLK Cycles
9
9
9
9
25
25
25
TABLE 1-4: INSTRUCTION SET FOR X 8 ORGANIZATION (93XX46A OR 93XX46C WITH ORG = 0)
Instruction
ERASE
ERAL
EWDS
EWEN
READ
WRITE
WRAL
SB
1
1
1
1
1
1
1
Opcode
11
00
00
00
10
01
00
A6
1
0
1
A6
A6
0
A5
0
0
1
A5
A5
1
Address
A4
X
X
X
A4
A4
X
A3
X
X
X
A3
A3
X
A2
X
X
X
A2
A2
X
A1
X
X
X
A1
A1
X
A0
X
X
X
A0
A0
X
Data In
—
—
—
—
—
D7 - D0
D7 - D0
Data Out
(RDY/BSY)
(RDY/BSY)
HIGH-Z
HIGH-Z
D7 - D0
(RDY/BSY)
(RDY/BSY)
Req. CLK Cycles
10
10
10
10
18
18
18
DS21749D-page 4
2003 Microchip Technology Inc.
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
2.0
FUNCTIONAL DESCRIPTION
2.3
Data Protection
When the ORG* pin is connected to V
CC
, the (x16)
organization is selected. When it is connected to
ground, the (x8) organization is selected. Instructions,
addresses and write data are clocked into the DI pin on
the rising edge of the clock (CLK). The DO pin is
normally held in a HIGH-Z state except when reading
data from the device, or when checking the READY/
BUSY status during a programming operation. The
READY/BUSY status can be verified during an Erase/
Write operation by polling the DO pin; DO low indicates
that programming is still in progress, while DO high
indicates the device is ready. DO will enter the HIGH-Z
state on the falling edge of CS.
All modes of operation are inhibited when V
CC
is below
a typical voltage of 1.5V for '93AA' and '93LC' devices
or 3.8V for '93C' devices.
The EWEN and EWDS commands give additional
protection against accidentally programming during
normal operation.
Note:
For added protection, an EWDS command
should be performed after every write
operation.
After power-up, the device is automatically in the
EWDS mode. Therefore, an
EWEN
instruction must be
performed before the initial
ERASE
or
WRITE
instruction
can be executed.
2.1
Start Condition
Block Diagram
V
CC
V
SS
Address
Decoder
The Start bit is detected by the device if CS and DI are
both high with respect to the positive edge of CLK for
the first time.
Before a Start condition is detected, CS, CLK, and DI
may change in any combination (except to that of a
Start condition), without resulting in any device
operation (READ, WRITE, ERASE, EWEN, EWDS,
ERAL, or WRAL). As soon as CS is high, the device is
no longer in Standby mode.
An instruction following a Start condition will only be
executed if the required opcode, address and data bits
for any particular instruction are clocked in.
Memory
Array
Address
Counter
Data Register
DI
ORG*
CS
CLK
Mode
Decode
Logic
Clock
Register
Output
Buffer
DO
2.2
Data In/Data Out (DI/DO)
It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a “bus conflict” to occur during the “dummy zero”
that precedes the READ operation, if A0 is a logic high
level. Under such a condition the voltage level seen at
Data Out is undefined and will depend upon the relative
impedances of Data Out and the signal source driving
A0. The higher the current sourcing capability of A0,
the higher the voltage at the Data Out pin. In order to
limit this current, a resistor should be connected
between DI and DO.
*ORG input is not available on A/B devices
2003 Microchip Technology Inc.
DS21749D-page 5
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