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SL2309NZSI-1HT

Description
Clock Buffer 0-140MHz 9 Fanout Buffer 3.3V
Categorysemiconductor    Analog mixed-signal IC   
File Size346KB,13 Pages
ManufacturerSilicon Laboratories
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SL2309NZSI-1HT Overview

Clock Buffer 0-140MHz 9 Fanout Buffer 3.3V

SL2309NZSI-1HT Parametric

Parameter NameAttribute value
Product CategoryClock Buffer
ManufacturerSilicon Laboratories
RoHSDetails
PackagingReel
Factory Pack Quantity2500
Unit Weight0.001764 oz
Not Recommended for New Designs
SL2309
Low Jitter and Skew 10 to 140 MHz Zero Delay Buffer (ZDB)
Key Features
10 to 140 MHz operating frequency range
Low output clock jitter:
140 ps-max cycle-to-cycle jitter
Low output-to-output skew: 150 ps-max
Low product-to-product skew: 400 ps-max
3.3 V power supply range
Low power dissipation:
26 mA-max at 66 MHz
44 mA –max at 133 MHz
One input drives 9 outputs organized as 4+4+1
Select mode to bypass PLL or tri-state outputs
SpreadThru™ PLL that allows use of SSCG
Standard and High-Drive options
Available in 16-pin SOIC and TSSOP packages
Available in Commercial and Industrial grades
Printers and MFPs
Digital Copiers
PCs and Work Stations
DTV
Routers, Switchers and Servers
Digital Embeded Systems
Description
The SL2309 is a low skew, low jitter and low power Zero
Delay Buffer (ZDB) designed to produce up to nine (9)
clock outputs from one (1) reference input clock, for high
speed clock distribution applications.
The product has an on-chip PLL which locks to the input
clock at CLKIN and receives its feedback internally from
the CLKOUT pin.
The SL2309 has two (2) clock driver banks each with four
(4) clock outputs. These outputs are controlled by two (2)
select input pins S1 and S2. When only four (4) outputs
are needed, four (4) bank-B output clock buffers can be tri-
stated to reduce power dissipation and jitter. The select
inputs can also be used to tri-state both banks A and B or
drive them directly from the input bypassing the PLL and
making the product behave like a Non-Zero Delay Fanout
Buffer (NZDB).
The high-drive (-1H) version operates up to 140MHz and
low drive (-1) version operates up to 100MHz at 3.3V.
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Applications
Benefits
Up to nine (9) distribution of input clock
Standard and High-Drive levels to control impedance
level, frequency range and EMI
Low power dissipation, jitter and skew
Low cost
Block Diagram
Low Power and
Low Jitter
PLL
MUX
CLKOUT
CLKIN
CLKA1
CLKA2
CLKA3
S2
CLKA4
S1
Input Selection
Decoding Logic
CLKB1
CLKB2
CLKB3
2
2
CLKB4
VDD
GND
Rev 2.0, May 12, 2008
Page 1 of 12
400 West Cesar Chavez, Austin, TX 78701
1 (512) 416-8500 1 (512) 416-9669
www.silabs.com

SL2309NZSI-1HT Related Products

SL2309NZSI-1HT SL2309NZSI-1T SL2309ZC-1T SL2309ZI-1T SL2309SC-1HT SL2309NZSC-1H
Description Clock Buffer 0-140MHz 9 Fanout Buffer 3.3V Clock Buffer 0-140MHz 9 Fanout Buffer 3.3V Hi Drive Clock Buffer 10-140MHz 9 Outputs ZDB 3.3V Clock Buffer 10-140MHz 9 Outputs ZDB 3.3V Clock Buffer 10-140MHz 9 Outputs ZDB 3.3V High Drive Clock Buffer 0-140MHz 9 Fanout Buffer 3.3V
Product Category Clock Buffer Clock Buffer Clock Buffer Clock Buffer Clock Buffer Clock Buffer
Manufacturer Silicon Laboratories Silicon Laboratories Silicon Laboratories Silicon Laboratories Silicon Laboratories Silicon Laboratories
RoHS Details Details Details Details Details Details
Packaging Reel Reel Reel Reel Reel Bulk
Factory Pack Quantity 2500 2500 2500 2500 2500 48
Unit Weight 0.001764 oz 0.001764 oz 0.001764 oz 0.001764 oz 0.001764 oz 0.001764 oz
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