CS5532/34-BS
24-bit
∆Σ
ADCs
with
Ultra-low-noise PGIA
Features
Chopper-stabilized PGIA (Programmable
Gain Instrumentation Amplifier, 1x to 64x)
–
6 nV/√Hz @ 0.1 Hz (No 1/f noise) at 64x
–
1200 pA Input Current with Gains >1
General Description
The CS5532/34 are highly integrated
∆Σ
Analog-to-Digi-
tal Converters (ADCs) which use charge-balance
techniques to achieve 24-bit performance. The ADCs
are optimized for measuring low-level unipolar or bipolar
signals in weigh scale, process control, scientific, and
medical applications.
To accommodate these applications, the ADCs come as
either two-channel (CS5532) or four-channel (CS5534)
devices and include a very low-noise, chopper-stabilized
instrumentation amplifier (6 nV/√Hz @ 0.1 Hz) with se-
lectable gains of 1×, 2×, 4×, 8×, 16×, 32×, and 64×.
These ADCs also include a fourth-order
∆Σ
modulator
followed by a digital filter which provides twenty selectable
output word rates of 6.25, 7.5, 12.5, 15, 25, 30, 50, 60, 100,
120, 200, 240, 400, 480, 800, 960, 1600, 1920, 3200, and
3840 Sps (MCLK = 4.9152 MHz).
To ease communication between the ADCs and a micro-
controller, the converters include a simple three-wire se-
rial interface which is SPI™ and Microwire™ compatible
with a Schmitt-trigger input on the serial clock (SCLK).
High dynamic range, programmable output rates, and
flexible power supply options makes these ADCs ideal
solutions for weigh scale and process control
applications.
ORDERING INFORMATION
See
page 47
Delta-sigma Analog-to-digital Converter
–
Linearity Error: 0.0007% FS
–
Noise-free Resolution: Up to 23 bits
Two- or Four-channel Differential MUX
Scalable Input Span via Calibration
–
±5 mV to differential ±2.5V
Scalable V
REF
Input: Up to Analog Supply
Simple Three-wire Serial Interface
–
SPI™ and Microwire™ Compatible
–
Schmitt Trigger on Serial Clock (SCLK)
R/W Calibration Registers Per Channel
Selectable Word Rates: 6.25 to 3,840 Sps
Selectable 50 or 60 Hz Rejection
Power Supply Configurations
–
VA+ = +5 V; VA- = 0 V; VD+ = +3 V to +5 V
–
VA+ = +2.5 V; VA- = -2.5 V; VD+ = +3 V to +5 V
–
VA+ = +3 V; VA- = -3 V; VD+ = +3 V
VA+
C1
C2
VREF+
VREF-
VD+
AIN1+
AIN1-
AIN2+
AIN2-
AIN3+
AIN3-
AIN4+
AIN4-
MUX
PGIA
1,2,4,8,16
32,64
DIFFERENTIAL
4
TH
ORDER
∆Σ
MODULATOR
CS
PROGRAMMABLE
SINC FIR FILTER
SERIAL
INTERFACE
SDI
SDO
SCLK
(CS5534
SHOWN)
CLOCK
GENERATOR
CALIBRATION
SRAM/CONTROL
LOGIC
LATCH
VA-
A0/GUARD
A1
OSC1
OSC2
DGND
http://www.cirrus.com
Copyright
©
Cirrus Logic, Inc. 2008
(All Rights Reserved)
OCT ‘08
DS755F3
CS5532/34-BS
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ..........................................................4
ANALOG CHARACTERISTICS..........................................................................4
TYPICAL RMS NOISE (NV) ...............................................................................7
TYPICAL NOISE-FREE RESOLUTION(BITS) ...................................................7
5 V DIGITAL CHARACTERISTICS ....................................................................8
3 V DIGITAL CHARACTERISTICS ....................................................................8
DYNAMIC CHARACTERISTICS ........................................................................9
ABSOLUTE MAXIMUM RATINGS .....................................................................9
SWITCHING CHARACTERISTICS ..................................................................10
2. GENERAL DESCRIPTION .......................................................................................12
2.1. Analog Input ....................................................................................................12
2.1.1. Analog Input Span .................................................................................... 13
2.1.2. Multiplexed Settling Limitations ............................................................13
2.1.3. Voltage Noise Density Performance .....................................................13
2.1.4. No Offset DAC ......................................................................................14
2.2. Overview of ADC Register Structure and Operating Modes ............................14
2.2.1. System Initialization ..............................................................................15
2.2.2. Serial Port Interface ..............................................................................22
2.2.3. Reading/Writing On-Chip Registers ......................................................23
2.3. Configuration Register .....................................................................................23
2.3.1. Power Consumption .............................................................................23
2.3.2. System Reset Sequence ......................................................................23
2.3.3. Input Short ............................................................................................24
2.3.4. Guard Signal .........................................................................................24
2.3.5. Voltage Reference Select .....................................................................24
2.3.6. Output Latch Pins .................................................................................24
2.3.7. Offset and Gain Select ..........................................................................25
2.3.8. Filter Rate Select ..................................................................................25
2.4. Setting up the CSRs for a Measurement .........................................................27
2.5. Calibration ........................................................................................................30
2.5.1. Calibration Registers ............................................................................30
2.5.2. Performing Calibrations ........................................................................31
2.5.3. Self Calibration .....................................................................................31
2.5.4. System Calibration ................................................................................32
2.5.5. Calibration Tips .....................................................................................32
2.5.6. Limitations in Calibration Range ...........................................................33
2.6. Performing Conversions ..................................................................................33
2.6.1. Single Conversion Mode .......................................................................33
2.6.2. Continuous Conversion Mode ..............................................................34
2.6.3. Examples of Using CSRs to Perform Conversions and Calibrations ....35
2.7. Using Multiple ADCs Synchronously ...............................................................36
2.8. Conversion Output Coding ..............................................................................36
2.9. Digital Filter ......................................................................................................38
2.10. Clock Generator ...............................................................................................39
2.11. Power Supply Arrangements ...........................................................................39
2.12. Getting Started ................................................................................................43
2.13. PCB Layout .....................................................................................................43
3. PIN DESCRIPTIONS ...............................................................................................44
4. SPECIFICATION DEFINITIONS ...............................................................................46
5. ORDERING INFORMATION .....................................................................................47
6. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION ..............47
7. PACKAGE DRAWINGS ...........................................................................................48
2
DS755F3
CS5532/34-BS
LIST OF FIGURES
Figure 1. SDI Write Timing (Not to Scale)............................................................................... 11
Figure 2. SDO Read Timing (Not to Scale)............................................................................. 11
Figure 3. Multiplexer Configuration ......................................................................................... 12
Figure 4. Input models for AIN+ and AIN- pins ....................................................................... 13
Figure 5. Measured Voltage Noise Density............................................................................. 13
Figure 6. CS5532/34 Register Diagram .................................................................................. 14
Figure 7. Command and Data Word Timing ........................................................................... 22
Figure 8. Guard Signal Shielding Scheme .............................................................................. 24
Figure 9. Input Reference Model when VRS = 1 .................................................................... 25
Figure 10. Input Reference Model when VRS = 0 .................................................................. 25
Figure 11. Self Calibration of Offset ........................................................................................ 32
Figure 12. Self Calibration of Gain .......................................................................................... 32
Figure 13. System Calibration of Offset .................................................................................. 32
Figure 14. System Calibration of Gain .................................................................................... 32
Figure 15. Synchronizing Multiple ADCs................................................................................. 36
Figure 16. Digital Filter Response (WR = 60 Sps) .................................................................. 38
Figure 18. 120 Sps Filter Phase Plot to 120 Hz ...................................................................... 38
Figure 17. 120 Sps Filter Magnitude Plot to 120 Hz ............................................................... 38
Figure 19. Z-Transforms of Digital Filters................................................................................ 38
Figure 20. On-chip Oscillator Model........................................................................................ 39
Figure 21. CS5532 Configured with a Single +5 V Supply ..................................................... 40
Figure 22. CS5532 Configured with ±2.5 V Analog Supplies.................................................. 41
Figure 23. CS5532 Configured with ±3 V Analog Supplies..................................................... 41
Figure 24. CS5532 Configured for Thermocouple Measurement ........................................... 42
Figure 25. Bridge with Series Resistors .................................................................................. 42
LIST OF TABLES
Table 1. Conversion Timing – Single Mode ............................................................................ 34
Table 2. Conversion Timing – Continuous Mode .................................................................... 35
Table 3. Command Byte Pointer ............................................................................................. 35
Table 4. Output Coding for 24-bit CS5532 and CS5534......................................................... 37
DS755F3
3
CS5532/34-BS
1. CHARACTERISTICS AND SPECIFICATIONS
ANALOG CHARACTERISTICS
(VA+, VD+ = 5 V ±5%; VREF+ = 5 V; VA-, VREF-, DGND = 0 V; MCLK = 4.9152 MHz;
OWR (Output Word Rate) = 60 Sps; Bipolar Mode; Gain = 32)
(See Notes 1 and 2.)
Parameter
Accuracy
Linearity Error
No Missing Codes
Bipolar Offset
Unipolar Offset
Offset Drift
Bipolar Full-scale Error
Unipolar Full-scale Error
Full-scale Drift
(Notes 3 and 4)
Min
-
24
-
-
-
-
-
-
Typ
±0.0007
-
±16
±32
640/G + 5
±8
±16
2
Max
±0.0015
-
±32
±64
-
±31
±62
-
Unit
%FS
Bits
LSB
24
LSB
24
nV/°C
ppm
ppm
ppm/°C
(Note 4)
Notes: 1. Applies after system calibration at any temperature within -40 °C ~ +85 °C.
2. Specifications guaranteed by design, characterization, and/or test. LSB is 24 bits.
3. This specification applies to the device only and does not include any effects by external parasitic
thermocouples. The PGIA contributes 5 nV of offset drift, and the modulator contributes 640/G nV of
offset drift, where G is the amplifier gain setting.
4. Drift over specified temperature range after calibration at power-up at 25 °C.
4
DS755F3
CS5532/34-BS
ANALOG CHARACTERISTICS
(See Notes 1 and 2.)
Parameter
Min
Typ
Max
Unit
Analog Input
Common Mode + Signal on AIN+ or AIN-Bipolar/Unipolar Mode
Gain = 1
VA-
-
Gain = 2, 4, 8, 16, 32, 64
(Note 5) VA- + 0.7
-
CVF Current on AIN+ or AIN-
Gain = 1
(Note 6, 7)
-
50
Gain = 2, 4, 8, 16, 32, 64
-
1200
Input Current Noise
Gain = 1
-
200
Gain = 2, 4, 8, 16, 32, 64
-
1
Input Leakage for Mux when Off (at 25 °C)
-
10
Off-channel Mux Isolation
-
120
Open Circuit Detect Current
100
300
Common Mode Rejection
dc, Gain = 1
-
90
dc, Gain = 64
-
130
50, 60 Hz
-
120
Input Capacitance
-
60
Guard Drive Output
-
20
Voltage Reference Input
Range
(VREF+) - (VREF-)
1
2.5
CVF Current
(Note 6, 7)
-
50
Common Mode Rejection
dc
-
120
50, 60 Hz
-
120
Input Capacitance
11
-
System Calibration Specifications
Full-scale Calibration Range
Bipolar/Unipolar Mode
3
-
Offset Calibration Range
Bipolar Mode
-100
-
Offset Calibration Range
Unipolar Mode
-90
-
(Continued)
VA+
VA+ - 1.7
-
-
-
-
-
-
-
-
-
-
-
-
(VA+)-(VA-)
-
-
-
22
110
100
90
V
V
nA
pA
pA/√Hz
pA/√Hz
pA
dB
nA
dB
dB
dB
pF
µA
V
nA
dB
dB
pF
%FS
%FS
%FS
Notes: 5. The voltage on the analog inputs is amplified by the PGIA, and becomes V
CM
±
Gain*(AIN+ - AIN-)/2 at
the differential outputs of the amplifier. In addition to the input common mode + signal requirements for
the analog input pins, the differential outputs of the amplifier must remain between (VA- + 0.1 V) and
(VA+ - 0.1 V) to avoid saturation of the output stage.
6. See the section of the data sheet which discusses input models.
7. Input current on AIN+ or AIN- (with Gain = 1), or VREF+ or VREF- may increase to 250 nA if operated
within 50 mV of VA+ or VA-. This is due to the rough charge buffer being saturated under these
conditions.
DS755F3
5
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