ZGP323LSP2008G datasheet, PDF - EEWORLD Datasheet

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ZGP323LSP2008G: Description8-bit Microcontrollers - MCU 8K Low Voltage OTP; CategoryThe embedded processor and controller Microcontrollers and processors; File Size926KB，107 Pages; ManufacturerZilog, Inc.; Websitehttps://www.zilog.com/; Environmental Compliance

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8-bit Microcontrollers - MCU 8K Low Voltage OTP

ZGP323LSP2008G Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Zilog, Inc.
Parts packaging code	DIP
package instruction	DIP, DIP20,.3
Contacts	20
Reach Compliance Code	unknown
Has ADC	NO
Address bus width
bit size	8
CPU series	Z8
maximum clock frequency	8 MHz
DAC channel	NO
DMA channel	NO
External data bus width
JESD-30 code	R-PDIP-T20
JESD-609 code	e3
length	25.905 mm
Humidity sensitivity level	3
Number of I/O lines	16
Number of terminals	20
Maximum operating temperature	70 °C
Minimum operating temperature
PWM channel	NO
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP20,.3
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	2.5/3.3 V
Certification status	Not Qualified
RAM (bytes)	237
rom(word)	8192
ROM programmability	OTPROM
Maximum seat height	4.49 mm
speed	8 MHz
Maximum slew rate	10 mA
Maximum supply voltage	3.6 V
Minimum supply voltage	2 V
Nominal supply voltage	3 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	MATTE TIN
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.62 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER
Base Number Matches	1

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Z8 GP

Microcontrollers

ZGP323H OTP MCU Family

Product Specification

PS023803-0305

ZiLOG Worldwide Headquarters • 532 Race Street • San Jose, CA 95126-3432

Telephone: 408.558.8500 • Fax: 408.558.8300 •

www.ZiLOG.com

ZGP323H

Product Specification

Table of Contents

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii

Development Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Standard Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

XTAL1 Crystal 1 (Time-Based Input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

XTAL2 Crystal 2 (Time-Based Output) . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Port 0 (P07–P00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Port 1 (P17–P10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Port 2 (P27–P20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Port 3 (P37–P30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RESET (Input, Active Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Expanded Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Counter/Timer Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Expanded Register File Control Registers (0D) . . . . . . . . . . . . . . . . . . . . . . . . 66

Expanded Register File Control Registers (0F) . . . . . . . . . . . . . . . . . . . . . . . . . 71

Standard Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

PS023803-0305

Table of Contents

ZGP323H

Product Specification

List of Figures

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Figure 33.

Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Counter/Timers Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

20-Pin PDIP/SOIC/SSOP/CDIP* Pin Configuration . . . . . . . . . . . . . . 5

28-Pin PDIP/SOIC/SSOP/CDIP* Pin Configuration . . . . . . . . . . . . . . 6

40-Pin PDIP/CDIP* Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . 7

48-Pin SSOP Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Test Load Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

AC Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Port 0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Port 1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Port 2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Port 3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Port 3 Counter/Timer Output Configuration . . . . . . . . . . . . . . . . . . . 24

Program Memory Map (32K OTP) . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Expanded Register File Architecture . . . . . . . . . . . . . . . . . . . . . . . . 28

Glitch Filter Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Transmit Mode Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

8-Bit Counter/Timer Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

T8_OUT in Single-Pass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

T8_OUT in Modulo-N Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Demodulation Mode Count Capture Flowchart . . . . . . . . . . . . . . . . 44

Demodulation Mode Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

16-Bit Counter/Timer Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

T16_OUT in Single-Pass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

T16_OUT in Modulo-N Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Ping-Pong Mode Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Output Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Interrupt Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Oscillator Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Port Configuration Register (PCON) (Write Only) . . . . . . . . . . . . . . 55

STOP Mode Recovery Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

PS023803-0305

List of Figures

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