AT25FS010N-SH27-T datasheet, PDF

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AT25FS010N-SH27-T: DescriptionFlash Memory 8 2.7V - 8-PH/ NIPDAU 2.7; Categorystorage storage; File Size531KB，24 Pages; ManufacturerAtmel (Microchip); Environmental Compliance

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AT25FS010N-SH27-T Overview

Flash Memory 8 2.7V - 8-PH/ NIPDAU 2.7

AT25FS010N-SH27-T Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Atmel (Microchip)
Parts packaging code	SOIC
package instruction	0.150 INCH, LEAD FREE AND HALOGEN FREE, PLASTIC, MS-012AA, SOIC-8
Contacts	8
Reach Compliance Code	unknown
ECCN code	EAR99
Maximum clock frequency (fCLK)	50 MHz
Durability	10000 Write/Erase Cycles
JESD-30 code	R-PDSO-G8
JESD-609 code	e4
length	4.9 mm
memory density	1048576 bit
Memory IC Type	FLASH
memory width	8
Humidity sensitivity level	1
Number of functions	1
Number of terminals	8
word count	131072 words
character code	128000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	128KX8
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP8,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Parallel/Serial	SERIAL
Peak Reflow Temperature (Celsius)	260
power supply	3/3.3 V
Programming voltage	2.7 V
Certification status	Not Qualified
Maximum seat height	1.75 mm
Serial bus type	SPI
Maximum standby current	0.00001 A
Maximum slew rate	0.045 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	40
type	NOR TYPE
width	3.9 mm
write protect	HARDWARE/SOFTWARE
Base Number Matches	1

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Features

•

Serial Peripheral Interface (SPI) Compatible

•

Supports SPI Modes 0 (0,0) and 3 (1,1)

•

– Datasheet describes Mode 0 Operation

50 MHz Clock Rate

Byte Mode and Page Mode Program (1 to 256 Bytes) Operations

Sector/Block/Page Architecture

– 256 byte Pages per Sector

– Eight 4 Kbyte Sectors per Block

– Four uniform 32 Kbyte Blocks

Self-timed Sector, Block and Chip Erase

Product Identification Mode with JEDEC Standard

Low-voltage Operation

– 2.7V (V

= 2.7V to 3.6V)

Hardware and Software Write Protection

– Device protection with Write Protect (WP) Pin

– Write Enable and Write Disable Instructions

– Software Write Protection:

• Upper 1/32, 1/16, 1/8, 1/4, 1/2 or Entire Array

Flexible Op Codes for Maximum Compatibility

Self-timed Program Cycle

– 30 µs/Byte Typical

Single Cycle Reprogramming (Erase and Program) for Status Register

High Reliability

– Endurance: 10,000 Write Cycles Typical

8-lead JEDEC 150mil SOIC and 8-lead Ultra Thin Small Array Package (SAP)

Die Sales: Waffer Form, Tape and Reel, and Bumped Waffers

•

High Speed

Small Sectored

SPI Flash

Memory

1M (131,072 x 8)

•

AT25FS010

Not Recommended

for New Design

See AT45DB011D

Description

The AT25FS010 provides 1,048,576 bits of serial reprogrammable Flash memory

organized as 131,072 words of 8 bits each. The device is optimized for use in many

industrial and commercial applications where low-power and low-voltage operation

are essential. The AT25FS010 is available in a space-saving 8-lead JEDEC SOIC and

8-lead Ultra Thin SAP packages.

Table 0-1.

Pin Name

SCK

GND

VCC

HOLD

Pin Configuration

Function

Chip Select

Serial Data Clock

Serial Data Input

Serial Data Output

Ground

Power Supply

Write Protect

Suspends Serial

Input

8-lead JEDEC SOIC

GND

VCC

HOLD

SCK

8-lead SAP

___

VCC

_____

HOLD 7

SCK 6

SI 5

1 CS

___

3 WP

4 GND

5167E–SFLSH–5/09

Bottom View

AT25FS010

2. Serial Interface Description

MASTER:

The device that generates the serial clock.

SLAVE:

Because the Serial Clock pin (SCK) is always an input, the AT25FS010 always oper-

ates as a slave.

TRANSMITTER/RECEIVER:

The AT25FS010 has separate pins designated for data transmis-

sion (SO) and reception (SI).

MSB:

The Most Significant Bit (MSB) is the first bit transmitted and received.

SERIAL OP-CODE:

After the device is selected with CS going low, the first byte will be

received. This byte contains the op-code that defines the operations to be performed.

INVALID OP-CODE:

If an invalid op-code is received, no data will be shifted into the

AT25FS010, and the serial output pin (SO) will remain in a high impedance state until the falling

edge of CS is detected again. This will reinitialize the serial communication.

CHIP SELECT:

The AT25FS010 is selected when the CS pin is low. When the device is not

selected, data will not be accepted via the SI pin, and the serial output pin (SO) will remain in a

high impedance state.

HOLD:

The HOLD pin is used in conjunction with the CS pin to select the AT25FS010. When

the device is selected and a serial sequence is underway, HOLD can be used to pause the serial

communication with the master device without resetting the serial sequence. To pause, the

HOLD pin must be brought low while the SCK pin is low. To resume serial communication, the

HOLD pin is brought high while the SCK pin is low (SCK may still toggle during HOLD). Inputs to

the SI pin will be ignored while the SO pin is in the high impedance state.

WRITE PROTECT:

The AT25FS010 has a write lockout feature that can be activated by assert-

ing the write protect pin (WP). When the lockout feature is activated, locked-out sectors will be

READ only. The write protect pin will allow normal read/write operations when held high. When

the WP is brought low and WPEN bit is “1”, all write operations to the status register are inhib-

ited. WP going low while CS is still low will interrupt a write to the status register. If the internal

status register write cycle has already been initiated, WP going low will have no effect on any

write operation to the status register. The WP pin function is blocked when the WPEN bit in the

status register is “0”. This will allow the user to install the AT25FS010 in a system with the WP

pin tied to ground and still be able to write to the status register. All WP pin functions are enabled

when the WPEN bit is set to “1”.

5167E–SFLSH–5/09

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