HCC40105B
HCF40105B
FIFO REGISTER
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INDEPENDENT ASYNCHRONOUS INPUTS
AND OUTPUTS
3-STATE OUTPUTS
EXPANDABLE IN EITHER DIRECTION
STATUS INDICATORS ON INPUT AND OUT-
PUT
RESET CAPABILITY
STANDARDIZED, SYMMETRICAL OUTPUT
CHARACTERISTICS
QUIESCENT CURRENT SPECIFIED AT 20V
FOR HCC DEVICE
5V, 10V, AND 15V PARAMETRIC RATINGS
INPUT CURRENT OF 100nA AT 18V AND 25°C
FOR HCC DEVICE
100% TESTED FOR QUIESCENT CURRENT
MEETS ALL REQUIREMENTS OF JEDEC TEN-
TATIVE STANDARD N
o
13A, ”STANDARD
SPECIFICATIONS FOR DESCRIPTION OF ”B”
SERIES CMOS DEVICES”
READY) indicates if the FIFO contains data. As the
earliest data are removed from the bottom of the data
stack (the output end), all data entered later will auto-
matically propagate (ripple) toward the output.
EY
(Plastic Package)
F
(Ceramic Package)
C1
(Chip Carrier)
ORDER CODES :
HCC40105BF
HCF40105BEY
HCF40105BC1
DESCRIPTION
The
HCC40105B
(extended temperature range) and
HCF40105B
(intermediate temperature range) are
monolithic integrated circuits, available in 16-lead dual
in-line plastic or ceramic package.
The
HCC/HCF40105B
is a low-power first-in-first-out
(FIFO) ”elastic” storage register that can store 16 4-bit
words. It is capable of handling input and output data
at different shifting rates. This feature makes it particu-
larly useful as a buffer between asynchronous sys-
tems. Each word position in the register is clocked by
a control flip-flop, which stores a marker bit. A ”1” sig-
nifies that the position’s data is filled and a ”0” denotes
a vacancy in that position. The control flip-flop detects
the state of the preceding flip-flop and communicates
its own status to the succeeding flip-flop. When a con-
trol flip-flop is in the ”0” state and sees a ”1” in the
preceding flip-flop, it generates a clock pulse that
transfers data from the preceding four data latches
into its own four data latches and resets the preceding
flip-flop to ”0”. The first and last control flip-flops have
buffered outputs. Since all empty locations ”bubble”
automatically to the input end, and all valid data ripple
through to the output end, the status of the first control
flip-flop (DATA-IN READY) indicates if the FIFO is full,
and the status of the last flip-flop (DATA-OUT
June 1989
PIN CONNECTIONS
1/12
HCC/HCF40105B
FUNCTIONAL DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DD
*
V
i
I
I
P
to t
Parameter
Supply Voltage :
HCC
Types
HC F
Types
Input Voltage
DC Input Current (any one input)
Total Power Dissipation (per package)
Dissipation per Output Transistor
for T
o p
= Full Package-temperature Range
Operating Temperature :
H CC
Types
H C F
Types
Storage Temperature
Value
– 0.5 to + 20
– 0.5 to + 18
– 0.5 to V
DD
+ 0.5
±
10
200
100
– 55 to + 125
– 40 to + 85
– 65 to + 150
Unit
V
V
V
mA
mW
mW
°C
°C
°C
T
op
T
stg
Stresses above those listed under ”Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for external periods may affect device reliability.
* All voltage values are referred to V
SS
pin voltage.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
DD
V
I
T
op
Parameter
Supply Voltage :
HC C
Types
H CF
Types
Input Voltage
Operating Temperature :
H CC
Types
H C F
Types
Value
3 to 18
3 to 15
0 to V
DD
– 55 to + 125
– 40 to + 85
Unit
V
V
V
°C
°C
2/12
HCC/HCF40105B
DYNAMIC ELECTRICAL CHARACTERISTICS
(T
amb
= 25
°C,
C
L
= 50 pF, R
L
= 200 kΩ,
typical temperature coefficient for all V
D D
values is 0.3 %/°C, all input rise and fall time = 20 ns)
Symbol
t
P HL
Parameter
Propagation Delay Time
Shift-out or Reset to Data-out
Ready
Propagation Delay Time
Shift-in to Data-in Ready
Test Conditions
V
D D
(V)
Min.
5
10
15
5
10
15
t
P ZH
, t
P ZL
Propagation Delay Time
3-state Control to Data-out
5
10
15
t
P HZ
, t
P L Z
Propagation Delay Time
3-State Control to Data-out
5
10
15
t
PLH
Ripple-through Delay Input to
Output
5
10
15
t
THL
, t
TL H
Transition Time
5
10
15
f
I
Shift-in or Shift-out Rate
5
10
15
t
WH
Shift-in Pulse Width
5
10
15
t
WL
Shift-out Pulse Width
5
10
15
t
r
Shift-in or Shift-out Rise Time
5
10
15
t
f
Shift-in Fall Time
5
10
15
t
f
Shift-out Fall Time
5
10
15
t
se tup
Data Setup Time
5
10
15
0
0
0
ns
200
80
60
360
160
100
Value
Typ.
185
90
65
160
65
45
140
60
40
100
50
40
2
1
0.7
100
50
40
1.5
3
4
100
40
30
180
80
50
15
15
15
15
15
15
15
5
5
µs
µs
µs
ns
ns
Max.
370
180
130
320
130
90
280
120
80
200
100
80
4
2
1.4
200
100
80
3
6
8
MHz
ns
µs
ns
ns
ns
ns
Unit
t
P HL
5/12
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