18-Port, 48-Lane, 240Gbps,
Gen2 RapidIO Switch
CPS-1848
Datasheet
Description
The CPS-1848 (80HCPS1848) is a
RapidIO Specification (Rev. 2.1)
compliant Central Packet Switch whose functionality is central to
routing packets for distribution among DSPs, processors, FPGAs,
other switches, or any other RapidIO-based devices. It can also be
used in RapidIO backplane switching. The CPS-1848 supports Serial
RapidIO (S-RIO) packet switching (unicast, multicast, and an optional
broadcast) from any of its 18 input ports to any of its 18 output ports.
Features
• RapidIO ports
—
48
bidirectional S-RIO lanes
— Port widths of 1x, 2x, and 4x allow up to 20 Gbps per port
— Port speeds selectable: 6.25, 5, 3.125, 2.5, or 1.25 Gbaud
— Support Level I defined short or long haul reach, and Level II
defined short-, medium-, or long-run reach for each PHY speed
— Error Management Extensions support
— Software-assisted error recovery, supporting hot swap
• I
2
C Interfaces
— Provides I
2
C port for maintenance and error reporting
— Master or Slave operation
— Master allows power-on configuration from external ROM
— Master mode configuration with external image compressing and
checksum
• Switch
—
240
Gbps peak throughput
— Non-blocking data flow architecture
— Configurable for Cut-Through or Store-and-Forward data flow
— Very low latency for all packet lengths and load conditions
— Internal queuing buffer and retransmit buffer
— Standard transmitter- or receiver-controlled flow control
— Global routing or Local Port routing capability
— Supports up to 40 simultaneous multicast masks, with broadcast
— Performance monitoring counters for performance and
diagnostics analysis. Per input port and output port counters
• SerDes
— Transmitter pre-emphasis and drive strength + receiver
equalization provides best possible signal integrity
— Embedded PRBS generation and detection with programmable
polynomials support Bit Error Rate testing
• Additional Information
— Packet Trace/Mirror. Each input port can copy all incoming
packets matching user-defined criteria to a “trace” output port.
— Packet Filter. Each input port can filter (drop) all incoming packets
matching user-defined criteria.
— Device configurable through any of S-RIO ports, I
2
C, or JTAG
— Full JTAG Boundary Scan Support (IEEE1149.1 and 1149.6)
—
Lidded/Lidless
784-FCBGA Package:
29
29 mm,
1.0 mm ball
pitch
Block Diagram
Quadrant 0
Lanes 0-3, 16-19, 32-35
Ports 0, 4, 8, 12, 16
Quadrant 3
Lanes 12-15, 28-31, 44-47
Ports 3, 7, 11, 15
CPS-1848
RapidIO Gen2
Switch Fabric
Event Management and Maintenance
Registers
I
2
C Controller
Ports 1, 5, 9, 13, 17
Lanes 4-7, 20-23, 36-39
Quadrant 1
JTAG Controller
Ports 2, 6, 10, 14
Lanes 8-11, 24-27, 40-43
Quadrant 2
Typical Applications
•
•
•
•
High-performance computing
Wireless
Defense and aerospace
Video and imaging
©2017 Integrated Device Technology, Inc.
1
June 26, 2017
CPS-1848 Datasheet
Table of Contents
1.
About This Document.................................................................................................................... 4
Introduction............................................................................................................................................................................................................ 4
Additional Resources............................................................................................................................................................................................. 4
Document Conventions and Definitions................................................................................................................................................................. 4
Revision History..................................................................................................................................................................................................... 4
Device Description ........................................................................................................................ 6
Specification Compliancy....................................................................................................................................................................................... 7
Functional Overview ..................................................................................................................... 7
Interface Overview........................................................................................................................ 8
S-RIO Ports ........................................................................................................................................................................................................... 8
I2C Bus .................................................................................................................................................................................................................. 8
JTAG TAP Port...................................................................................................................................................................................................... 8
Interrupt (IRQ_N) ................................................................................................................................................................................................... 8
Reset (RST_N) ...................................................................................................................................................................................................... 8
Clock (REF_CLK_P/N) .......................................................................................................................................................................................... 8
Rext (REXT_N/P) .................................................................................................................................................................................................. 9
Speed Select (SPD[2:0])........................................................................................................................................................................................ 9
Quadrant Config (QCFG[7:0])................................................................................................................................................................................ 9
Frequency Select (FSEL[1:0]) ............................................................................................................................................................................... 9
Multicast (MCAST)................................................................................................................................................................................................. 9
Configuration Pins ....................................................................................................................... 10
Speed Select Pins SPD[2:0]................................................................................................................................................................................ 10
Quadrant Configuration Pins QCFG[7:0]............................................................................................................................................................. 10
Absolute Maximum Ratings ........................................................................................................ 14
Recommended Operating Conditions ......................................................................................... 15
AC Test Conditions...................................................................................................................... 16
Power Consumption .................................................................................................................... 18
2.
3.
4.
5.
6.
7.
8.
9.
10. I
2
C Bus ......................................................................................................................................... 19
I
2
C Master Mode and Slave Mode....................................................................................................................................................................... 19
I
2
C Device Address ............................................................................................................................................................................................. 19
Signaling.............................................................................................................................................................................................................. 20
Read/Write Figures.............................................................................................................................................................................................. 21
I
2
C DC Electrical Specifications........................................................................................................................................................................... 23
I
2
C AC Electrical Specifications........................................................................................................................................................................... 24
I
2
C Timing Waveforms......................................................................................................................................................................................... 25
11. Interrupt (IRQ_N) Electrical Specifications ................................................................................ 26
12. Configuration (Static) Pin Specification ..................................................................................... 27
13. S-RIO Ports .................................................................................................................................. 28
Overview.............................................................................................................................................................................................................. 28
Definition of Amplitude and Swing....................................................................................................................................................................... 29
1.25, 2.5, and 3.125 Gbaud LP-Serial Links........................................................................................................................................................ 30
Level I Electrical Specification ............................................................................................................................................................................. 30
5 and 6.25 Gbaud LP-Serial Links....................................................................................................................................................................... 37
Level II Electrical Specifications .......................................................................................................................................................................... 37
©2017 Integrated Device Technology, Inc.
2
June 26, 2017
CPS-1848 Datasheet
14. Reference Clock .......................................................................................................................... 47
Reference Clock Electrical Specifications ........................................................................................................................................................... 47
15. Reset (RST_N) Specification ....................................................................................................... 49
16. JTAG Interface ............................................................................................................................ 50
Description........................................................................................................................................................................................................... 50
IEEE 1149.1 (JTAG) and IEEE 1149.6 (AC Extest) Compliance ........................................................................................................................ 50
System Logic TAP Controller Overview............................................................................................................................................................... 50
Signal Definitions ................................................................................................................................................................................................. 51
Test Data Register (DR) ...................................................................................................................................................................................... 52
Boundary Scan Registers.................................................................................................................................................................................... 52
Instruction Register (IR)....................................................................................................................................................................................... 55
EXTEST............................................................................................................................................................................................................... 56
Configuration Register Access (Revision A/B) .................................................................................................................................................... 58
Configuration Register Access (Revision C)........................................................................................................................................................ 60
JTAG DC Electrical Specifications....................................................................................................................................................................... 63
JTAG AC Electrical Specifications....................................................................................................................................................................... 64
JTAG Timing Waveforms..................................................................................................................................................................................... 65
17. Pinout and Pin Listing ................................................................................................................. 66
Pinout — Top View .............................................................................................................................................................................................. 66
Pin Listing ............................................................................................................................................................................................................ 67
18. Package Specifications .............................................................................................................. 77
Package Physical Specifications ......................................................................................................................................................................... 77
Package Outline Drawings .................................................................................................................................................................................. 78
Thermal Characteristics....................................................................................................................................................................................... 83
19. Ordering Information ................................................................................................................... 85
©2017 Integrated Device Technology, Inc.
3
June 26, 2017
CPS-1848 Datasheet
1.
About This Document
Introduction
The
CPS-1848 Datasheet
provides hardware information about the CPS-1848, such as electrical and packaging characteristics. It is intended for
hardware engineers who are designing system interconnect applications with the device.
Additional Resources
The
CPS-1848 User Manual
describes the functionality and configuration capabilities of the device. In addition, there are many other resources
available that support the CPS-1848. For more information, please contact IDT for support.
Document Conventions and Definitions
This document uses the following conventions and definitions:
•
To indicate signal states:
–
Differential signals use the suffix “_P” to indicate the positive half of a differential pair.
–
Differential signals use the suffix “_N” to indicate the negative half of a differential pair.
–
Non-differential signals use the suffix “_N” to indicate an active-low state.
•
•
•
•
•
To define buses, the most significant bit (MSB) is on the left and least significant bit (LSB) is on the right. No leading zeros are included.
To represent numerical values, either decimal, binary, or hexadecimal formats are used. The binary format is as follows: 0bDDD, where “D”
represents either 0 or 1; the hexadecimal format is as follows: 0xDD, where “D” represents the hexadecimal digit(s); otherwise, it is decimal.
Unless otherwise denoted, a byte refers to an 8-bit quantity; a word refers to a 32-bit quantity, and a double word refers to an 8-byte (64-bit)
quantity. This is in accordance with RapidIO convention.
A bit is set when its value is 0b1. A bit is cleared when its value is 0b0.
A read-only register, bit, or field is one that can be read but not modified.
This symbol indicates important configuration information or suggestions.
This symbol indicates procedures or operating levels that may result in misuse or damage to
the device.
Revision History
June 26, 2017
• Updated the
Package Outline Drawings;
no technical changes
• Updated the
Ordering Information
April 4, 2016
•
•
•
•
•
•
•
Added an R_X2 symbol to
Table 20
Updated the
Package Physical Specifications
Updated
Heat Sink Requirement and Analysis
Added HMH, HMG, and BLG part numbers to
Ordering Information
Updated the note associated with
VDD3A
(pin AD24)
Changed the maximum 3.3V supply requirement to 3.47V in
Table 6
and note 2 below the table
Added two cautionary notes about lane reordering to
Pin Listing
June 12, 2013
June 8, 2012
©2017 Integrated Device Technology, Inc.
4
June 26, 2017
CPS-1848 Datasheet
April 2, 2012
•
•
•
•
•
•
•
Added JTAG configuration register access information for Revision C in
Configuration Register Access (Revision C)
Updated the JTAG version number for Revision C
Added a BR FCBGA (Lidded) package option to
Package Outline Drawings
Added new thermal data for the BR FCBGA package to
Thermal Characteristics
Added BR FCBGA package information to
Ordering Information
Loosened the Clock Input signal rise/fall minimum time specification
Added an additional note to the power sequencing requirements
December 9, 2011
©2017 Integrated Device Technology, Inc.
5
June 26, 2017
京公网安备 11010802033920号
EEWORLD
