PIC32MX1XX/2XX
32-bit Microcontrollers (up to 128 KB Flash and 32 KB SRAM) with
Audio and Graphics Interfaces, USB, and Advanced Analog
Operating Conditions
• 2.3V to 3.6V, -40ºC to +105ºC, DC to 40 MHz
Timers/Output Compare/Input Capture
• Five General Purpose Timers:
- Five 16-bit and up to two 32-bit Timers/Counters
• Five Output Compare (OC) modules
• Five Input Capture (IC) modules
• Peripheral Pin Select (PPS) to allow function remap
• Real-Time Clock and Calendar (RTCC) module
Core: 40 MHz MIPS32
®
M4K
®
•
•
•
•
MIPS16e
®
mode for up to 40% smaller code size
1.56 DMIPS/MHz (Dhrystone 2.1) performance
Code-efficient (C and Assembly) architecture
Single-cycle (MAC) 32x16 and two-cycle 32x32 multiply
Clock Management
•
•
•
•
•
0.9% internal oscillator
Programmable PLLs and oscillator clock sources
Fail-Safe Clock Monitor (FSCM)
Independent Watchdog Timer
Fast wake-up and start-up
Communication Interfaces
• USB 2.0-compliant Full-speed OTG controller
• Two UART modules (10 Mbps)
- Supports LIN 2.0 protocols and IrDA
®
support
• Two 4-wire SPI modules (20 Mbps)
• Two I
2
C modules (up to 1 Mbaud) with SMBus support
• Peripheral Pin Select (PPS) to allow function remap
• Parallel Master Port (PMP)
Power Management
•
•
•
•
Low-power management modes (Sleep, Idle)
Integrated Power-on Reset and Brown-out Reset
0.5 mA/MHz dynamic current (typical)
20
μA
I
PD
current (typical)
Direct Memory Access (DMA)
• Four channels of hardware DMA with automatic data
size detection
• Two additional channels dedicated for USB
• Programmable Cyclic Redundancy Check (CRC)
Audio Interface Features
• Data communication: I
2
S, LJ, RJ, DSP modes
• Control interface: SPI and I
2
C™
• Master clock:
- Generation of fractional clock frequencies
- Can be synchronized with USB clock
- Can be tuned in run-time
Input/Output
•
•
•
•
15 mA source/sink on all I/O pins
5V-tolerant pins
Selectable open drain, pull-ups, and pull-downs
External interrupts on all I/O pins
Advanced Analog Features
• ADC Module:
- 10-bit 1.1 Msps rate with one S&H
- Up to 10 analog inputs on 28-pin devices and 13
analog inputs on 44-pin devices
• Flexible and independent ADC trigger sources
• Charge Time Measurement Unit (CTMU):
- Supports mTouch™ capacitive touch sensing
- Provides high-resolution time measurement (1 ns)
- On-chip temperature measurement capability
• Comparators:
- Up to three Analog Comparator modules
- Programmable references with 32 voltage points
Qualification and Class B Support
• AEC-Q100 REVG (Grade 2 -40ºC to +105ºC) planned
• Class B Safety Library, IEC 60730
Debugger Development Support
•
•
•
•
In-circuit and in-application programming
4-wire MIPS
®
Enhanced JTAG interface
Unlimited program and six complex data breakpoints
IEEE 1149.2-compatible (JTAG) boundary scan
Packages
Type
Pin Count
I/O Pins (up to)
Contact/Lead Pitch
Dimensions
Note:
SOIC
28
21
1.27
17.90x7.50x2.65
SSOP
28
21
0.65
10.2x5.3x2
SPDIP
28
21
0.100''
1.365x.285x.135''
28
21
0.65
6x6x0.9
QFN
44
34
0.65
8x8x0.9
36
25
0.50
5x5x0.9
VTLA
44
34
0.50
6x6x0.9
TQFP
44
34
0.80
10x10x1
All dimensions are in millimeters (mm) unless specified.
©
2011 Microchip Technology Inc.
Preliminary
DS61168C-page 1
PIC32MX1XX/2XX
TABLE 1:
PIC32MX1XX GENERAL PURPOSE FAMILY FEATURES
Timers
(2)
/Capture/Compare
10-bit 1 Msps ADC (Channels)
DMA Channels
(Programmable/Dedicated)
Remappable Peripherals
Program Memory (KB)
(1)
External Interrupts
(3)
USB On-The-Go (OTG)
Analog Comparators
Data Memory (KB)
Remappable Pins
SPI/I
2
S
UART
PIC32MX110F016B
PIC32MX110F016C
PIC32MX110F016D
28
36
44
16+3
16+3
16+3
4
4
4
20
24
32
5/5/5
5/5/5
5/5/5
2
2
2
2
2
2
5
5
5
3
3
3
N
N
N
2
2
2
Y
Y
Y
4/2
4/2
4/2
Y
Y
Y
10
12
13
Y
Y
Y
21
25
34
Y
Y
Y
SOIC,
SSOP,
SPDIP,
QFN
VTLA
VTLA,
TQFP,
QFN
SOIC,
SSOP,
SPDIP,
QFN
VTLA
VTLA,
TQFP,
QFN
SOIC,
SSOP,
SPDIP,
QFN
VTLA
VTLA,
TQFP,
QFN
SOIC,
SSOP,
SPDIP,
QFN
VTLA
VTLA,
TQFP,
QFN
PIC32MX120F032B
PIC32MX120F032C
PIC32MX120F032D
28
36
44
32+3
32+3
32+3
8
8
8
20
24
32
5/5/5
5/5/5
5/5/5
2
2
2
2
2
2
5
5
5
3
3
3
N
N
N
2
2
2
Y
Y
Y
4/2
4/2
4/2
Y
Y
Y
10
12
13
Y
Y
Y
21
25
34
Y
Y
Y
PIC32MX130F064B
PIC32MX130F064C
PIC32MX130F064D
28
36
44
64+3
64+3
64+3
16
16
16
20
24
32
5/5/5
5/5/5
5/5/5
2
2
2
2
2
2
5
5
5
3
3
3
N
N
N
2
2
2
Y
Y
Y
4/2
4/2
4/2
Y
Y
Y
10
12
13
Y
Y
Y
21
25
34
Y
Y
Y
PIC32MX150F128B
PIC32MX150F128C
PIC32MX150F128D
Note 1:
2:
3:
28 128+3 32
36 128+3 32
44 128+3 32
20
24
32
5/5/5
5/5/5
5/5/5
2
2
2
2
2
2
5
5
5
3
3
3
N
N
N
2
2
2
Y
Y
Y
4/2
4/2
4/2
Y
Y
Y
10
12
13
Y
Y
Y
21
25
34
Y
Y
Y
This device features 3 KB of boot Flash memory.
Four out of five timers are remappable.
Four out of five external interrupts are remappable.
DS61168C-page 2
Preliminary
©
2011 Microchip Technology Inc.
Packages
I/O Pins
Device
CTMU
RTCC
JTAG
I
2
C™
PMP
Pins
PIC32MX1XX/2XX
TABLE 2:
PIC32MX2XX USB FAMILY FEATURES
Timers
(2)
/Capture/Compare
10-bit 1 Msps ADC (Channels)
DMA Channels
(Programmable/Dedicated)
Remappable Peripherals
Program Memory (KB)
(1)
External Interrupts
(3)
USB On-The-Go (OTG)
Analog Comparators
Data Memory (KB)
Remappable Pins
SPI/I
2
S
UART
PIC32MX210F016B
PIC32MX210F016C
PIC32MX210F016D
28
36
44
16+3
16+3
16+3
4
4
4
19
23
31
5/5/5
5/5/5
5/5/5
2
2
2
2
2
2
5
5
5
3
3
3
Y
Y
Y
2
2
2
Y
Y
Y
4/2
4/2
4/2
Y
Y
Y
9
12
13
Y
Y
Y
19
23
33
Y
Y
Y
SOIC,
SSOP,
SPDIP,
QFN
VTLA
VTLA,
TQFP,
QFN
SOIC,
SSOP,
SPDIP,
QFN
VTLA
VTLA,
TQFP,
QFN
SOIC,
SSOP,
SPDIP,
QFN
VTLA
VTLA,
TQFP,
QFN
SOIC,
SSOP,
SPDIP,
QFN
VTLA
VTLA,
TQFP,
QFN
PIC32MX220F032B
PIC32MX220F032C
PIC32MX220F032D
28
36
44
32+3
32+3
32+3
8
8
8
19
23
31
5/5/5
5/5/5
5/5/5
2
2
2
2
2
2
5
5
5
3
3
3
Y
Y
Y
2
2
2
Y
Y
Y
4/2
4/2
4/2
Y
Y
Y
9
12
13
Y
Y
Y
19
23
33
Y
Y
Y
PIC32MX230F064B
PIC32MX230F064C
PIC32MX230F064D
28
36
44
64+3
64+3
64+3
16
16
16
19
5/5/5
5/5/5
5/5/5
2
2
2
2
2
2
5
5
5
3
3
3
Y
Y
Y
2
2
2
Y
Y
Y
4/2
4/2
4/2
Y
Y
Y
9
12
13
Y
Y
Y
19
23
33
Y
Y
Y
23
31
PIC32MX250F128B
PIC32MX250F128C
PIC32MX250F128D
Note 1:
2:
3:
28 128+3 32
36 128+3 32
44 128+3 32
19
5/5/5
5/5/5
5/5/5
2
2
2
2
2
2
5
5
5
3
3
3
Y
Y
Y
2
2
2
Y
Y
Y
4/2
4/2
4/2
Y
Y
Y
9
12
13
Y
Y
Y
19
23
33
Y
Y
Y
23
31
This device features 3 KB of boot Flash memory.
Four out of five timers are remappable.
Four out of five external interrupts are remappable.
©
2011 Microchip Technology Inc.
Preliminary
DS61168C-page 3
Packages
I/O Pins
Device
CTMU
RTCC
JTAG
I
2
C™
PMP
Pins
PIC32MX1XX/2XX
Pin Diagrams
28-Pin SOIC, SPDIP, SSOP
(1,2)
= Pins are up to 5V tolerant
MCLR
V
REF
+/CV
REF
+/AN0/C3INC/RPA0/CTED1/RA0
V
REF
-/CV
REF
-/AN1/RPA1/CTED2/RA1
PGED1/AN2/C1IND/C2INB/C3IND/RPB0/RB0
PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/RB1
AN4/C1INB/C2IND/RPB2/SDA2/CTED13/RB2
AN5/C1INA/C2INC/RTCC/RPB3/SCL2/RB3
V
SS
OSC1/CLKI/RPA2/RA2
OSC2/CLKO/RPA3/PMA0/RA3
SOSCI/RPB4/RB4
SOSCO/RPA4/T1CK/CTED9/PMA1/RA4
V
DD
PGED3/RPB5/PMD7/RB5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AV
DD
AV
SS
AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15
CV
REF
/AN10/C3INB/RPB14/SCK1/CTED5/PMWR/RB14
AN11/RPB13/CTPLS/PMRD/RB13
AN12/PMD0/RB12
PGEC2/TMS/RPB11/PMD1/RB11
PGED2/RPB10/CTED11/PMD2/RB10
V
CAP
V
SS
TDO/RPB9/SDA1/CTED4/PMD3/RB9
TCK/RPB8/SCL1/CTED10/PMD4/RB8
TDI/RPB7/CTED3/PMD5/INT0/RB7
PGEC3/RPB6/PMD6/RB6
PIC32MX120F032B
PIC32MX120F016B
PIC32MX130F064B
PIC32MX150F128B
MCLR
PGED3/V
REF
+/CV
REF
+/AN0/C3INC/RPA0/CTED1/PMD7/RA0
PGEC3/V
REF
-/CV
REF
-/AN1/RPA1/CTED2/PMD6/RA1
PGED1/AN2/C1IND/C2INB/C3IND/RPB0/PMD0/RB0
PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/PMD1/RB1
AN4/C1INB/C2IND/RPB2/SDA2/CTED13/PMD2/RB2
AN5/C1INA/C2INC/RTCC/RPB3/SCL2/PMWR/RB3
V
SS
OSC1/CLKI/RPA2/RA2
OSC2/CLKO/RPA3/PMA0/RA3
SOSCI/RPB4/RB4
SOSCO/RPA4/T1CK/CTED9/PMA1/RA4
V
DD
TMS/RPB5/USBID/RB5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AV
DD
AV
SS
AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15
CV
REF
/AN10/C3INB/RPB14/VBUSON/SCK1/CTED5/RB14
AN11/RPB13/CTPLS/PMRD/RB13
V
USB
PGEC2/RPB11/D-/RB11
PGED2/RPB10/D+/CTED11/RB10
V
CAP
V
SS
TDO/RPB9/SDA1/CTED4/PMD3/RB9
TCK/RPB8/SCL1/CTED10/PMD4/RB8
TDI/RPB7/CTED3/PMD5/INT0/RB7
V
BUS
Note
1:
2:
The RPn pins can be used by remappable peripherals. See
Table 1
for the available peripherals and
Section 11.3 “Peripheral
Pin Select”
for restrictions.
Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See
Section 11.0 “I/O Ports”
for more
information.
DS61168C-page 4
Preliminary
PIC32MX220F032B
PIC32MX220F016B
PIC32MX230F064B
PIC32MX250F128B
©
2011 Microchip Technology Inc.
PIC32MX1XX/2XX
Pin Diagrams (Continued)
28-Pin QFN
(1,2,3)
= Pins are up to 5V tolerant
V
REF
+/CV
REF
+/AN0/C3INC/RPA0/CTED1/RA0
MCLR
28
27
26
25
24
23
PGED1/AN2/C1IND/C2INB/C3IND/RPB0/RB0
PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/RB1
AN4/C1INB/C2IND/RPB2/SDA2/CTED13/RB2
AN5/C1INA/C2INC/RTCC/RPB3/SCL2/RB3
V
SS
OSC1/CLKI/RPA2/RA2
OSC2/CLKO/RPA3/PMA0/RA3
22
CV
REF
/AN10/C3INB/RPB14/SCK1/CTED5/PMWR/RB14
AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15
V
REF
-/CV
REF
-/AN1/RPA1/CTED2/RA1
AV
DD
AV
SS
1
2
3
4
5
6
7
10
11
12
13
14
8
9
21
20
AN11/RPB13/CTPLS/PMRD/RB13
AN12/PMD0/RB12
PGEC2/TMS/RPB11/PMD1/RB11
PGED2/RPB10/CTED11/PMD2/RB10
V
CAP
V
SS
TDO/RPB9/SDA1/CTED4/PMD3/RB9
PIC32MX120F032B
PIC32MX120F016B
PIC32MX130F064B
PIC32MX150F128B
19
18
17
16
15
SOSCO/RPA4/T1CK/CTED9/PMA1/RA4
SOSCI/RPB4/RB4
V
DD
Note
1:
2:
3:
The RPn pins can be used by remappable peripherals. See
Table 1
for the available peripherals and
Section 11.3 “Peripheral
Pin Select”
for restrictions.
Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See
Section 11.0 “I/O Ports”
for more
information.
The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to V
SS
externally.
©
2011 Microchip Technology Inc.
Preliminary
TCK/RPB8/SCL1/CTED10/PMD4/RB8
PGED3/RPB5/PMD7/RB5
PGEC3/RPB6/PMD6/RB6
TDI/RPB7/CTED3/PMD5/INT0/RB7
DS61168C-page 5
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