DATASHEET
CD4051BMS, CD4052BMS, CD4053BMS
CMOS Analog Multiplexers/Demultiplexers*
FN3316
Rev 0.00
December 1992
Features
• Logic Level Conversion
• High-Voltage Types (20V Rating)
• CD4051BMS Signal 8-Channel
• CD4052BMS Differential 4-Channel
• CD4053BMS Triple 2-Channel
• Wide Range of Digital and Analog Signal Levels:
- Digital 3V to 20V
- Analog to 20Vp-p
• Low ON Resistance: 125 (typ) Over 15Vp-p Signal
Input Range for VDD - VEE = 15V
• High OFF Resistance: Channel Leakage of
100pA
(typ) at VDD - VEE = 18V
• Logic Level Conversion:
- Digital Addressing Signals of 3V to 20V (VDD - VSS
= 3V to 20V)
- Switch Analog Signals to 20Vp-p (VDD - VEE = 20V);
See Introductory Text
• Matched Switch Characteristics: RON = 5 (typ) for
VDD - VEE = 15V
• Very Low Quiescent Power Dissipation Under All Digi-
tal Control Input and Supply Conditions: 0.2W (typ)
at VDD - VSS = VDD - VEE = 10V
• Binary Address Decoding on Chip
• 5V, 10V and 15V Parametric Ratings
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1A at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25
o
C
• Break-Before-Making Switching Eliminates Channel
Overlap
Description
CD4051BMS, CD4052BMS and CD4053BMS analog multi-
plexers/demultiplexers are digitally controlled analog
switches having low ON impedance and very low OFF leak-
age current. Control of analog signals up to 20V peak-to-
peak can be achieved by digital signal amplitudes of 4.5V to
20V (if VDD-VSS = 3V, a VDD-VEE of up to 13V can be con-
trolled; for VDD-VEE level differences above 13V, a VDD-
VSS of at least 4.5V is required). For example, if VDD =
+4.5V, VSS = 0, and VEE = -13.5V, analog signals from -
13.5V to +4.5V can be controlled by digital inputs of 0 to 5V.
These multiplexer circuits dissipate extremely low quiescent
power over the full VDD-VSS and VDD-VEE supply voltage
ranges, independent of the logic state of the control signals.
When a logic “1” is present at the inhibit input terminal all
channels are off.
The CD4051BMS is a single 8 channel multiplexer having
three binary control inputs, A, B, and C, and an inhibit input.
The three binary signals select 1 of 8 channels to be turned
on, and connect one of the 8 inputs to the output.
The CD4052BMS is a differential 4 channel multiplexer hav-
ing two binary control inputs, A and B, and an inhibit input.
The two binary input signals select 1 of 4 pairs of channels to
be turned on and connect the analog inputs to the outputs.
The CD4053BMS is a triple 2 channel multiplexer having
three separate digital control inputs, A, B, and C, and an
inhibit input. Each control input selects one of a pair of chan-
nels which are connected in a single pole double-throw con-
figuration.
The CD4051BMS, CD4052BMS and CD4053BMS are supplied
in these 16 lead outline packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
*CD4051B Only
*H4X
H1E
H6W
†CD4052B, CD4053 Only
†H4T
Applications
• Analog and Digital Multiplexing and Demultiplexing
• A/D and D/A Conversion
• Signal Gating
* When these devices are used as demultiplexers the “CHANNEL
IN/OUT” terminals are the outputs and the “COMMON OUT/IN”
terminals are the inputs.
FN3316 Rev 0.00
December 1992
Page 1 of 12
CD4051BMS, CD4052BMS, CD4053BMS
Pinouts
CD4051BM
TOP VIEW
CHANNELS
IN/OUT
4
6
1
2
3
4
5
6
16 VDD
15 2
14 1
13 0
12 3
11 A
10 B
9 C
CHANNELS
IN/OUT
Y CHANNELS
IN/OUT
0
2
1
2
3
4
5
CD4052BMS
TOP VIEW
16 VDD
15 2
14 1
X CHANNELS
IN/OUT
COM OUT/IN
CHANNELS
IN/OUT
7
5
INH
COMMON “Y” OUT/IN
Y CHANNELS
IN/OUT
3
1
13 COMMON “X” OUT/IN
12 0
11 3
10 A
9 B
X CHANNELS
IN/OUT
INH 6
VEE
VSS
7
8
VEE 7
VSS 8
CD4053BMS
TOP VIEW
by
IN/OUT
bx
cy
OUT/IN CX or CY
IN/OUT CX
INH
VEE
VSS
1
2
3
4
5
6
7
8
16 VDD
15 OUT/IN bx or by
14 OUT/IN ax or ay
13 ay
12 ax
11 A
10 B
9 C
IN/OUT
Functional Diagrams
CHANNEL IN/OUT
7
16
VDD
4
6
2
5
5
4
1
3
12
2
15
1
14
0
13
TG
*
A
11
TG
TG
*
B
10
LOGIC
LEVEL
CONVERSION
*
C
9
BINARY
TO
1 OF 8
DECODER
WITH
INHIBIT
TG
3
TG
COMMON
OUT/IN
TG
*
INH
6
TG
TG
VDD
8
VSS
7
VEE
* ALL INPUTS PROTECTED BY
STANDARD CMOS PROTECTION
NETWORK
VSS
CD4051BMS
FN3316 Rev 0.00
December 1992
Page 2 of 12
CD4051BMS, CD4052BMS, CD4053BMS
Functional Diagrams
(Continued)
X CHANNELS IN/OUT
3
11
2
15
1
14
0
12
TG
16
VDD
TG
TG
COMMON X
OUT/IN
13
*
A
10
LOGIC
LEVEL
CONVERSION
BINARY
TO
1 OF 4
DECODER
WITH
INHIBIT
TG
TG
3
COMMON Y
OUT/IN
*
B
9
TG
*
INH
6
TG
TG
1
0
8
VSS
7
VEE
5
1
2
2
4
3
Y CHANNELS IN/OUT
CD4052BMS
VDD
* ALL INPUTS PROTECTED BY
STANDARD CMOS PROTECTION
NETWORK
VSS
BINARY TO 1 OF 2
DECODERS WITH
INHIBIT
16
VDD
IN/OUT
cy
3
cx
5
by
1
bx
2
ay
13
ax
12
OUT/IN
ax or ay
14
TG
OUT/IN
bx or by
15
TG
LOGIC
LEVEL
CONVERSION
TG
*
A
11
*
B
10
TG
*
C
9
TG
OUT/IN
cx or cy
4
*
INH
6
TG
8
VSS
7
VEE
CD4053BMS
FN3316 Rev 0.00
December 1992
Page 3 of 12
CD4051BMS, CD4052BMS, CD4053BMS
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input
10mA
Operating Temperature Range . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . . -65
o
C to +150
o
C
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265
o
C
At Distance 1/16 1/32 Inch (1.59mm
0.79mm) from case for
10s Maximum
Reliability Information
Thermal Resistance . . . . . . . . . . . . . . . .
ja
jc
o
C/W
o
C/W
Ceramic DIP and FRIT Package . . . . . 80
20
Flatpack Package . . . . . . . . . . . . . . . . 70
o
C/W
20
o
C/W
Maximum Package Power Dissipation (PD) at +125
o
C
For TA = -55
o
C to +100
o
C (Package Type D, F, K) . . . . . . 500mW
For TA = +100
o
C to +125
o
C (Package Type D, F, K) . . . . . Derate
Linearity at 12mW/
o
C to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175
o
C
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
(NOTE 1)
VDD = 20V, VIN = VDD or GND
VDD = 18V, VIN = VDD or GND
Input Leakage Current
IIL
VIN = VDD or GND
VDD = 20
VDD = 18V
Input Leakage Current
IIH
VIN = VDD or GND
VDD = 20
VDD = 18V
On-State Resistance
RL = 10K Returned to
VDD - VSS/2
RON
VDD = 5V
VIS = VSS to VDD
VDD = 10V
VIS = VSS to VDD
VDD = 15V
VIS = VSS to VDD
N Threshold Voltage
P Threshold Voltage
Functional
(Note 4)
VNTH
VPTH
F
VDD = 10V, ISS = -10A
VSS = 0V, IDD = 10A
VDD = 2.8V, VIN = VDD or GND
VDD = 20V, VIN = VDD or GND
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
Input Voltage Low
(Note 2)
Input Voltage High
(Note 2)
Input Voltage Low
(Note 2)
Input Voltage High
(Note 2)
Off Channel Leakage
Any Channel OFF
Or
All Channels Off
(Common Out/In)
VIL
VIH
VIL
VIH
IOZL
VDD = 5V = VIS thru 1k,
VEE = VSS
RL = 1k to VSS, |IIS| < 2A
OFF Channels
VDD = 15V = VIS thru 1K
VEE = VSS
RL = 1K to VSS, |ISS|, <2A
On All OFF Channels
VIN = VDD or GND
VOUT = 0V
VIN = VDD or GND
VOUT = VDD
VDD = 20V
VDD = 18V
IOZH
VDD = 20V
VDD = 18V
NOTES: 1. All voltages referenced to device GND, 100% testing being
implemented.
2. Go/No Go test with limits applied to inputs.
GROUP A
SUBGROUPS
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
1
1
7
7
8A
8B
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1
2
3
1
2
3
LIMITS
TEMPERATURE
+25
o
C
+125 C
-55
o
C
+25
o
C
+125 C
-55
o
C
+25
o
C
+125 C
-55
o
C
C
+25
o
-55
o
o
o
o
MIN
-
-
-
-100
-1000
-100
-
-
-
-
-
-
-
-
-
-
-
-
-2.8
0.7
MAX
10
1000
10
-
-
-
100
1000
100
1050
1300
800
400
550
310
240
320
220
-0.7
2.8
UNITS
A
A
A
nA
nA
nA
nA
nA
nA
V
V
V
+125 C
C
C
+25
o
-55
o
o
+125 C
C
+25
o
C
+125 C
-55
o
C
+25
o
C
+25 C
+25
o
+25
o
C
C
o
o
o
VOH > VOL <
VDD/2 VDD/2
+125 C
-55
o
C
+25
o
C, +125
o
C, -55
o
C
+25
o
C, +125
o
C, -55
o
C
+25
o
C, +125
o
C, -55
o
C
+25
o
C, +125
o
C, -55
o
C
+25
o
C
+125
o
C
-55
o
C
+25 C
+125
o
C
-55
o
C
o
o
-
3.5
-
11
-0.1
-1.0
-0.1
-
-
-
1.5
-
4
-
-
-
-
0.1
1.0
0.1
V
V
V
V
A
A
A
A
A
A
3. For accuracy, voltage is measured differentially to VDD. Limit
is 0.050V max.
4. VDD = 2.8V/3.0V, RL = 200k to VDD
VDD = 20V/18V, RL = 10k to VDD
FN3316 Rev 0.00
December 1992
Page 4 of 12
CD4051BMS, CD4052BMS, CD4053BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP A
SUBGROUPS TEMPERATURE
9
10, 11
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
LIMITS
MIN
-
-
MAX
720
972
UNITS
ns
ns
PARAMETER
Propagation Delay
(Note 1)
Address to Signal Out
Channels On or Off
Propagation Delay
(Note 1)
Inhibit to Signal Out
(Channel Turning On)
Propagation Delay
(Note 1)
Inhibit to Signal Out
(Channel Turning Off)
NOTES:
SYMBOL
TPHL
TPLH
CONDITIONS
(Notes 1, 2)
VDD = 5V, VIN = VDD or GND
VEE = VSS = 0V
TPZH
TPZL
VDD = 5V, VIN = VDD or GND
VEE = VSS = 0V
9
10, 11
-
-
720
972
ns
ns
TPHZ
TPLZ
VDD = 5V, VIN = VDD or GND
VEE = VSS = 0V
9
10, 11
-
-
450
608
ns
ns
1. -55
o
C and +125
o
C limits guaranteed, 100% testing being implemented.
2. CL = 50pF, RL = 10K, Input TR, TF < 20ns.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
VDD = 5V, VIN = VDD or GND
NOTES
1, 2
TEMPERATURE
-55 C, +25 C
+125
o
C
VDD = 10V, VIN = VDD or GND
1, 2
-55
o
C, +25
o
C
+125
o
C
VDD = 15V, VIN = VDD or GND
1, 2
-55
o
C, +25
o
C
+125
o
C
Input Voltage Low
Input Voltage High
Propagation Delay
Address to Signal Out
(Channels On or Off)
VIL
VIH
TPHL
TPLH
VDD = VIS = 10V, VEE = VSS
RL = 1K to VSS
|IIS|, 2A On/Off Channel
1, 2
1, 2
1, 2, 3
1, 2, 3
1, 2, 3
VEE = VSS = 0V
1, 2, 3
1, 2, 3
1, 2, 3
VEE = VSS = 0V
1, 2, 3
1, 2, 3
1, 2, 3
1, 2
+25
o
C, +125
o
C,
-55
o
C
+25
o
C, +125
o
C,
-55
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
o
o
MIN
-
-
-
-
-
-
-
+7
-
-
-
-
-
-
-
-
-
-
MAX
5
150
10
300
10
600
3
-
320
240
450
320
240
400
210
160
300
7.5
UNITS
A
A
A
A
A
A
V
V
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
VDD = 10V
VDD = 15V
VDD = 5V
VEE = -5V
VEE = VSS = 0V
Propagation Delay
Inhibit to Signal Out
(Channel Turning On)
TPZH
TPZL
VDD = 10V
VDD = 15V
VDD = 5V
VEE = -10V
Propagation Delay
Inhibit to Signal Out
(Channel Turning Off)
TPHZ
TPLZ
VDD = 10V
VDD = 15V
VDD = 5V
VEE = -15V
Input Capacitance
NOTES:
CIN
Any Address or Inhibit Input
+25
o
C
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are char-
acterized on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 10K, Input TR, TF < 20ns.
FN3316 Rev 0.00
December 1992
Page 5 of 12
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