OMC 932723248
Hitachi Single-Chip Microcomputer
H8/534, H8/536
HD6475348R, HD6435348R
HD6475368R, HD6435368R
HD6475348S, HD6435348S
HD6475368S, HD6435368S
Hardware Manual
ADE-602-038B
Preface
The H8/534 and H8/536 are high-performance single-chip Hitachi-original microcomputers,
featuring a high-speed CPU with 16-bit internal data paths and a full complement of on-chip
supporting modules. They are ideal microcontrollers for a wide variety of medium-scale devices,
including both office and industrial equipment and consumer products.
The CPU has a general-register architecture. Its instruction set is highly orthogonal and is
optimized for fast execution of programs coded in the high-level C language. For further speed,
the existing 10-MHz lineup has been extended to include high-speed versions that operate at
16 MHz. Low-voltage versions that operate at 3 V and 2.7 V have also been developed.
On-chip facilities include large RAM and ROM memories, numerous timers, serial I/O, an A/D
converter, I/O ports, and other functions for compact implementation of high-performance
application systems.
H8/534 and H8/536 are available in both a ZTAT™ version* with on-chip PROM, ideal for the
early stages of production or for products with frequently-changing specifications, and a masked-
ROM version suitable for volume production.
This manual gives a hardware description of the H8/534 and H8/536. For details of the instruction
set, refer to the
H8/500 Series Programming Manual,
which applies to all chips in the H8/500
Series.
* ZTAT (Zero Turn-Around Time) is a trademark of Hitachi, Ltd.
2
Contents
Section 1 Overview
1.1
1.2
1.3
Features ··································································································································1
Block Diagram ·······················································································································5
Pin Arrangements and Functions ···························································································6
1.3.1 Pin Arrangement ·········································································································6
1.3.2 Pin Functions ··············································································································9
Section 2 MCU Operating Modes and Address Space
2.1
2.2
2.3
Overview ······························································································································23
Mode Descriptions ···············································································································24
Address Space Map ··············································································································25
2.3.1 Page Segmentation ····································································································25
2.3.2 Page 0 Address Allocations ······················································································26
Mode Control Register (MDCR) ·························································································27
2.4
Section 3 CPU
3.1
Overview ······························································································································31
3.1.1 Features ·····················································································································31
3.1.2 Address Space ···········································································································32
3.1.3 Register Configuration ······························································································33
CPU Register Descriptions ··································································································34
3.2.1 General Registers ······································································································34
3.2.2 Control Registers ······································································································35
3.2.3 Initial Register Values ·······························································································40
Data Formats ························································································································41
3.3.1 Data Formats in General Registers ···········································································41
3.3.2 Data Formats in Memory ··························································································42
Instructions ···························································································································44
3.4.1 Basic Instruction Formats ·························································································44
3.4.2 Addressing Modes ····································································································45
3.4.3 Effective Address Calculation ··················································································47
Instruction Set ······················································································································50
3.5.1 Overview ···················································································································50
3.5.2 Data Transfer Instructions ·························································································52
3.5.3 Arithmetic Instructions ·····························································································53
3.5.4 Logic Operations ·······································································································54
3.5.5 Shift Operations ········································································································55
3.5.6 Bit Manipulations ······································································································56
3.5.7 Branching Instructions ······························································································57
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.5.8 System Control Instructions ······················································································59
3.5.9 Short-Format Instructions ·························································································62
Operating Modes ··················································································································62
3.6.1 Minimum Mode ········································································································62
3.6.2 Maximum Mode ········································································································63
Basic Operational Timing ····································································································63
3.7.1 Overview ···················································································································63
3.7.2 On-Chip Memory Access Cycle ···············································································64
3.7.3 Pin States during On-Chip Memory Access ·····························································65
3.7.4 Register Field Access Cycle (Addresses H'FE80 to H'FFFF) ··································66
3.7.5 Pin States during Register Field Access (Addresses H'FE80 to H'FFFF) ················67
3.7.6 External Access Cycle ······························································································ 68
CPU States ···························································································································69
3.8.1 Overview ···················································································································69
3.8.2 Program Execution State ···························································································71
3.8.3 Exception-Handling State ·························································································71
3.8.4 Bus-Released State ····································································································72
3.8.5 Reset State ·················································································································77
3.8.6 Power-Down State ····································································································77
Programming Notes ·············································································································78
3.9.1 Restriction on Address Location ···············································································78
Section 4 Exception Handling
4.1
Overview ······························································································································79
4.1.1 Types of Exception Handling and Their Priority ······················································79
4.1.2 Hardware Exception-Handling Sequence ·································································80
4.1.3 Exception Factors and Vector Table ·········································································80
Reset ····································································································································83
4.2.1 Overview ···················································································································83
4.2.2 Reset Sequence ·········································································································83
4.2.3 Stack Pointer Initialization ························································································84
Address Error ·······················································································································87
4.3.1 Illegal Instruction Prefetch ························································································87
4.3.2 Word Data Access at Odd Address ···········································································87
4.3.3 Off-Chip Address Access in Single-Chip Mode ·······················································87
Trace ····································································································································88
Interrupts ······························································································································88
Invalid Instruction ················································································································91
Trap Instructions and Zero Divide ·······················································································91
Cases in Which Exception Handling is Deferred ·································································91
4.8.1 Instructions that Disable Interrupts ···········································································91
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.8.2 Disabling of Exceptions Immediately after a Reset ··················································92
4.8.3 Disabling of Interrupts after a Data Transfer Cycle ··················································92
4.9 Stack Status after Completion of Exception Handling ························································93
4.9.1 PC Value Pushed on Stack for Trace,
Interrupts, Trap Instructions, and Zero Divide Exceptions ·······································95
4.9.2 PC Value Pushed on Stack for Address Error and Invalid
Instruction Exceptions ······························································································95
4.10 Notes on Use of the Stack ····································································································95
Section 5 Interrupt Controller
5.1
Overview ······························································································································97
5.1.1 Features ·····················································································································97
5.1.2 Block Diagram ··········································································································98
5.1.3 Register Configuration ······························································································99
Interrupt Types ·····················································································································99
5.2.1 External Interrupts ····································································································99
5.2.2 Internal Interrupts ····································································································101
5.2.3 Interrupt Vector Table ·····························································································102
Register Descriptions ·········································································································104
5.3.1 Interrupt Priority Registers A to F (IPRA to IPRF) ················································104
5.3.2 Timing of Priority Setting ·······················································································105
Interrupt Handling Sequence ·····························································································105
5.4.1 Interrupt Handling Flow ·························································································105
5.4.2 Stack Status after Interrupt Handling Sequence ·····················································108
5.4.3 Timing of Interrupt Exception-Handling Sequence ················································109
Interrupts During Operation of the Data Transfer Controller ············································109
Interrupt Response Time ····································································································112
5.2
5.3
5.4
5.5
5.6
Section 6 Data Transfer Controller
6.1
Overview ····························································································································113
6.1.1 Features ···················································································································113
6.1.2 Block Diagram ········································································································113
6.1.3 Register Configuration ····························································································114
Register Descriptions ·········································································································115
6.2.1 Data Transfer Mode Register (DTMR) ···································································115
6.2.2 Data Transfer Source Address Register (DTSR) ····················································116
6.2.3 Data Transfer Destination Register (DTDR) ·························································116
6.2.4 Data Transfer Count Register (DTCR) ···································································116
6.2.5 Data Transfer Enable Registers A to F (DTEA to DTEF) ······································117
Data Transfer Operation ·····································································································118
6.3.1 Data Transfer Cycle ································································································118
6.2
6.3
Linux and Android
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